• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.13-18
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• 2024

This paper proposes a circuit utilizing auto zero technology to minimize offset and enhance accuracy in the reference generator and comparator. As evidence, a comparison between pre and post auto zero usage revealed a reduction of approximately 90% in standard deviation. The proposed circuit was implemented using a 55nm CMOS process, with an input frequency of 781.2 Hz. It achieves an Effective Number of Bits (ENOB) of 8.01 bits and a Signal-to-Noise Distortion Ratio (SNDR) of 49.98 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.933-940
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• 2021

The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.60-64
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• 2004

In this paper, we implemented a real-time remote home monitoring system which we have ported the Linux OS and HTTP(Hypertext Transfer Protocol) web server. The GoAhead web server was ported using by ARM cross compiler. And then we used the analog to digital converter ADC0809 for sensing the vii able input signal at widely separated home. We have implemented linux device driver for ADC(Analog to Digital Convertor) and CGI-C(Common Gateway Interface - C language) application program using Client pull method for monitoring real-time changing data. The factor of monitoring is temperature, intensity of illumination and gas's existence. And this system has ability which check the status of out door and gas valve. We have designed the embedded web server system for home emergency monitoring in low cost.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.260-264
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• 2005

This paper describes the ultra precise position control of servo motor using sinusoidal encoder based on 'Arcsine Interpolation Method'. First, the paper theoretically analyzes and verify throughout experiments, the relationship between A/D converter input ripple and the total resolution to measure the precise position. Second, this paper presents a way to compensate the total gain and offset error by utilizing a low cost programmable differential amp, by which without any special expensive equipments they are easily on-line tuned and effectively compensated. Lastly, it was compared to servomotor position control characteristics using digital incremental 50,000ppr encoder. The test results show that, with much cheaper sinusoidal encoder, the proposed method exhibits better performance both in position control and ASD applications than the 50,000ppr optical encoder.

• Journal of Biosystems Engineering
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• v.11 no.1
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• pp.8-16
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• 1986

This study was carried out to develop a microcomputer-based data acquisition system for engine performance test. A low-cost data acquisition system was developed utilizing an "APPLE II PLUS" microcomputer. The developed system consists of microcomputer, RPM counter included frequency-to-voltage converter, preamplifier for two load cells and 8-bit analog-to-digital converter with 16 chnnels. The system simultaneously measures engine speed by means of photointerrupter, torque and fuel consumption by means of load cells with variable sample numbers, sampling intervals and repetitions. The system collects, processes and provides data for storing on the $4{\frac{1}{4}}$ inch floppy disk as well as for writing out on the printer.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.