• Science of Emotion and Sensibility
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• v.13 no.1
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• pp.197-206
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• 2010

For an emotion retrieval system implementation to support pedestrian navigation, coordinating the pedestrian emotion model with the system user's emotion is considered a key component. This study proposes a new method for capturing the user's model that corresponds to the pedestrian emotion model and examines the validity of the method. In the first phase, a database comprising a set of interior images that represent hypothetical destinations was developed. In the second phase, 10 subjects were recruited and asked to evaluate on navigation and satisfaction toward each interior image in five rounds of navigation experiments. In the last phase, the subjects' feedback data was used for of the pedestrian emotion model, which is called ‘learning' in this study. After evaluations by the subjects, the learning effect was analyzed by the following aspects: recall ratio, precision ratio, retrieval ranking, and satisfaction. Findings of the analysis verify that all four aspects significantly were improved after the learning. This study demonstrates the effectiveness of the learning algorithm for the proposed pedestrian emotion model. Furthermore, this study demonstrates the potential of such pedestrian emotion model to be well applicable in the development of various mobile contents service systems dealing with visual images such as commercial interiors in the future.

• Science of Emotion and Sensibility
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• v.13 no.4
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• pp.635-646
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• 2010

This article focuses on Funology and a new classified application system based on concept of language and thought which are formed by body experience. It is defined by Funology Body as that. Funology Body is classifying and searching system which are consisted of a body, world (environment), and device tool. The body is sectioned by Brain, Eyes, Ears, Nose, Mouth, Hand, Torso, Feet, and Heart according as parts of the human body. This allows intuiting and experience searching as making classified system connected to the application relationship with concept of an each part of body. The Brain of the body is sub-classified by Book, Account, Business, Memory, Education, Search, and Aphorism to imply the application with thought. The Eyes take Video, Photography, and Broadcast for visibility. The Ears is categorized as Music, Instrument, Audio, and Radio for hearing. The Nose gets Perfume, Smell for olfactory sense. The Mouth is sectioned by Food, SNS, Chatting, Email, and Blog for eating and communication. The Hand sorts into Games, Kits, and Editing to handle, create, and play. The Torso is grouped by Health, Medical, Dance, Sport, Fashion, and Testyuorself related by protecting internal and meaning of the body core. The Feet is classified by Travel, Transportation, Map, and Outdoor for moving and concept of expanding the terrain. The Heart is consisted of Fear, Anger, Joy, Sadness, Acceptance, Disgust, Expectation, and Surprise for a human feeling. Beyond that, the World takes News, Time, Weather, Map, Fortune, and Shop, and Device tool gets Interface, Utilities. The Funology Body has a unique characteristic of giving intuitive and sensuous pleasure and reflection of users' attitude and taste for changing application flexibly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.1
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• pp.13-20
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• 2005

In this paper, I recognized Korean isolated words using CVEM which is suggested by M. Bilginer et al. CVEM is an algorithm which is easy to extract the common properties from training voice signals and also doesn't need complex calculation. In addition CVEM shows high accuracy in recognition results. But, CVEM has couple of problems which are impossible to use for many training voices and no discriminant information among extracted common vectors. To get the optimal common vectors from certain voice classes, various voices should be used for training. But CVEM is impossible to get continuous high accuracy in recognition because CVEM has a limitation to use many training voices and the absence of discriminant information among common vectors can be the source of critical errors. To solve above problems and improve recognition rate, k-clustering subspace method and DCVEM suggested. And did various experiments using voice signal database made by ETRI to prove the validity of suggested methods. The result of experiments shows improvements in performance. And with proposed methods, all the CVEM problems can be solved with out calculation problem.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.67-73
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• 2015

In a distribution of digital image, there is a serious problem that is the image alteration by a forger. For the problem solution, this paper proposes the forensic decision algorithm of a median filtering (MF) image using the feature vector based on a coefficient of variation (c.v.) of Fourier transform. In the proposed algorithm, we compute Fourier transform (FT) coefficients of row and column line respectively of an image first, then c.v. between neighboring lines is computed. Subsquently, 10 Dim. feature vector is defined for the MF detection. On the experiment of MF detection, the proposed scheme is compared to MFR (Median Filter Residual) and Rhee's MF detection schemes that have the same 10 Dim. feature vector both. As a result, the performance is excellent at Unaltered, JPEG (QF=90), Down scaling (0.9) and Up scaling (1.1) images, and it showed good performance at Gaussian filtering ($3{\times}3$) image. However, in the performance evaluation of all measured items of the proposed scheme, AUC (Area Under ROC (Receiver Operating Characteristic) Curve) by the sensitivity and 1-specificity approached to 1 thus, it is confirmed that the grade of the performance evaluation is rated as 'Excellent (A)'.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.