• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.42 no.1
• /
• pp.13-20
• /
• 2005

In this paper, I recognized Korean isolated words using CVEM which is suggested by M. Bilginer et al. CVEM is an algorithm which is easy to extract the common properties from training voice signals and also doesn't need complex calculation. In addition CVEM shows high accuracy in recognition results. But, CVEM has couple of problems which are impossible to use for many training voices and no discriminant information among extracted common vectors. To get the optimal common vectors from certain voice classes, various voices should be used for training. But CVEM is impossible to get continuous high accuracy in recognition because CVEM has a limitation to use many training voices and the absence of discriminant information among common vectors can be the source of critical errors. To solve above problems and improve recognition rate, k-clustering subspace method and DCVEM suggested. And did various experiments using voice signal database made by ETRI to prove the validity of suggested methods. The result of experiments shows improvements in performance. And with proposed methods, all the CVEM problems can be solved with out calculation problem.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.152-159
• /
• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.8
• /
• pp.67-73
• /
• 2015

In a distribution of digital image, there is a serious problem that is the image alteration by a forger. For the problem solution, this paper proposes the forensic decision algorithm of a median filtering (MF) image using the feature vector based on a coefficient of variation (c.v.) of Fourier transform. In the proposed algorithm, we compute Fourier transform (FT) coefficients of row and column line respectively of an image first, then c.v. between neighboring lines is computed. Subsquently, 10 Dim. feature vector is defined for the MF detection. On the experiment of MF detection, the proposed scheme is compared to MFR (Median Filter Residual) and Rhee's MF detection schemes that have the same 10 Dim. feature vector both. As a result, the performance is excellent at Unaltered, JPEG (QF=90), Down scaling (0.9) and Up scaling (1.1) images, and it showed good performance at Gaussian filtering ($3{\times}3$) image. However, in the performance evaluation of all measured items of the proposed scheme, AUC (Area Under ROC (Receiver Operating Characteristic) Curve) by the sensitivity and 1-specificity approached to 1 thus, it is confirmed that the grade of the performance evaluation is rated as 'Excellent (A)'.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.11
• /
• pp.86-94
• /
• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.82-92
• /
• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.65-74
• /
• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.443-451
• /
• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the HCI Society of Korea
• /
• v.5 no.2
• /
• pp.15-24
• /
• 2010

A Digilog Book is an augmented reality (AR) based next generation publication supporting both sentimental analog emotions and digitized multi-sensory feedbacks by combining a conventional printed book and digital contents. As a Digilog Book authoring software, ARtalet provides an intuitive authoring environment through 3D user interface in AR environment. In this paper, we suggest ARtalet authoring environment based trajectory editing method to generate and manipulate a movement path of an augmented 3D object on the Digilog Book. Specifically, the translation points of the 3D manipulation prop is examined to determine that the point is a proper control point of a trajectory. Then the interpolation using splines is conducted to reconstruct the trajectory with smoothed form. The dynamic score based selection method is also exploited to effectively select small and dense control points of the trajectory. In an experimental evaluation our method took the same time and generated a similar amount of errors as the usual approach, but reduced the number of control points needed by over 90%. The reduced number of control points can properly reconstruct a movement path and drastically decrease the number of control point selections required for movement path modification. For control manipulation, the task completion time was reduced and there was less hand movement needed than with conventional method. Our method can be applicable to drawing or curve editing method in immersive In-Situ AR based education, game, design, animation, simulation application domains.

• Journal of Korea Game Society
• /
• v.8 no.3
• /
• pp.43-50
• /
• 2008

UI design is growing in meaning and form itself through the development of hardware and contents. And it makes users accept its interface as a extension of the body and mind because of the substantial rapport of the user and contents with developing of device and graphic. In this study, we analyzed user interface in a view of digital storytelling by observing of its role within user and contents. Not only this, classifying and investigating story elements in the games for forming the theoretical basis of storytelling UI are enforced. For the case study of UI, we choose the game, Diablo, Half-Life, and Homeworld because the game is suitable for the application of node-type storytelling and effectively uses graphic and input unit. This analysis explains the interface has the contents data that divided or shared and it means the interface performs its part of story nodes, which are extracted from the story, and choice. And we analogized that the story elemental can be substituted and used practically for interface because the stories made through the thing that users and developers are in the space of coexistence by the interface. Storytelling UI will be a good way to make a most intriguing piece as a joyful spontaneous complex that use story node. It is worth by reason of making by user and discovering live inner story so that it can approach to the substance of the story.

• The Journal of the Korea Contents Association
• /
• v.11 no.2
• /
• pp.268-275
• /
• 2011

21C digital culture is now affecting the life of arts and development through our system, as well as body arts and body painting. Body painting is not has been focused through our lives in 21stcentury as one genre. UV body painting is from short to long wave length that demonstrates to us the dimension by science and lighting showing more than 8 colors that are better off being set. From this research the theory of body painting considerate characteristics and vision for it. From the researchers line, dots, and side shows the UV body painting as a one piece of art and analyzing the 3D theory and once again showing vision through what it's affecting to their result.' UV body painting is usage of floral paints and using so called 'black light' that shows the short and long term wavelength that provides the 3D material, but first, this is different from normal body painting like dots, like, and layers shows more thoroughly and shows focused motive and you can easily tell the difference. As of all UV body painting is showing more 3D vision more than the design itself. From all this research, to all the body painters we await the future practical theory to be used and for the better future.