• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2609-2612
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• 2003

This paper describes a 64 channel signal generator/analyzer module that is useful for verification and testing of digital circuits. It can perform logic analyzer function and signal generator function at the same time. The 64 Channel module is implemented with single FPGA chip for miniaturization, and an USB interface is used to increase portability of the module. Multiple modules can be used in parallel for the verification of large scale circuits. Moreover, since the module is implemented as a PC based system, one can configure convenient GUI(Graphic User Interface) environment.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.350-364
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• 2008

Single frequency network (SFN) design based on the Advanced Television Systems Committee (ATSC) specification, a terrestrial digital television (DTV) system, normally causes a interference problem, among signals from multiple transmitters or repeaters. To solve this, the ATSC recommended practice (RP) introduces a transmitter identification (TxID) signal embedded in a signal from each transmitter or repeater. A TxID signal analyzer is then used to detect the TxID signal, and following the analysis results, a SFN design can be adjusted. This paper discusses the generation and usages of Kasami sequence, is used the TxID signal. The configuration of the TxID signal analyzer to efficiently detect TxID signal is proposed and the results of theoretical performance analysis are provided. Moreover, computer simulation and laboratory test results are provided to evaluate the performance of TxID signal analyzer and the theoretical performance analysis.

• Progress in Medical Physics
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• v.3 no.1
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• pp.71-78
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• 1992

This study describes the design of the biophysiological signal processing analyzer which can collect and analyze the biosignal raw data. System hardware is consisted of the IBM PC AT. pre-amplifier. AID converter, Counter/Timer. and RS-232C processor. Biophysiological signal data were processed by the software digital filter. FFT and graphic processing routine. The tachogram and FFT of the the peak to peak interval time was accomplished by the Graphic user interface software using the biophysiological signal processed data. Using this system. the powerspectrum of the heart rate variability during the long term could be observed. Experimental results of this system approach our purpose. which is improved the cost performance. easy to use. reducing raw-data noise and optimizing model for digital filter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.127-137
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• 2009

This paper is proposed that in-output Digital module is acquired a vibration signal of a rotating machinery by Data Acquisition System. The module is designed to get ride of nose through low pass filter on the vibration signal from sensors and set the gain value for being able to sampling AC to DC, and also the sampled data by sampler and the conversed data by DIP/FPGA is supplied to the analyzer for analysis at a software tool. The DIP(Digital Signal Processor) of the Digital input/output Board makes Average voltage, Peak to Peak voltage, RMS(Root Mean Square) and Gap voltage, also FFT(Fast Fourier Transform) for rotating vibration diagnosis.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.27-33
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• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.479-483
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• 1997

In general, motor parameters can be divided into mechanical/electrical parameters and harmonic parameters. Mechanical/electrical parameters identification of motor have been studying systematically for a long time. But, systematical study on harmonic parameters analysis for efficient motor drive system are very poor. The goal of this paper is to propose analyzing method of harmonic parameters for motor drive system with various experimental graphic screens and numerical results and to develope harmonic parameters analyzer. A developed analyzer is made up 586-PC and DSP (digital signal processor) board, motor drive system, power and harmonic parameters analyzing software for windows. Harmonic parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis results are visualized by 3-D current coordinates, and it is compared and evaluated with conventional time/frequency domain. To verify the validity of the proposed system, 1/4HP capacitor run type single phase induction motor and thyristor speed controller is used for analyzing. Harmonic parameters of motor drive system is analyzed and verified, with varying fire angle of thyristor speed controller, and the proposed approach is to confirm validity.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.4
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• pp.362-368
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• 2001

The goal of this paper is development ofa DSP based three phase power quality analyzer. Power analysis algorithm is a correlation function and it is accomplished using stand alone type TMS320C31 DSP(digital signal processor)board. Results of power analysis are displayed by LCD and D/A converter on the proposed system. Finally, this paper also goes on to discuss the performance of an instrument prototype, compared with one of those foreign models, both in terms of accuracy and speed of measurement.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.175-179
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• 2003

In this paper, we developed a DTV RF (Radio frequency) capture, analysis, and regeneration system adapting digital signal processing and high speed hard disk interfacing techniques and analyzed characteristics of captured RF signal. This system can be used in the various field of DTV transmission because this system can capture the receiving real DTV signals and analyze captured RF signals that contain the complex characteristics of the real-world RF environments and regenerate it in a laboratory without the performance degradation. The system can capture and replay the DTV RF signals in real-time on hard disk. Therefore, there is no limit for the amount of captured data with in the installed storage capacity. We can expect various possible applications for this system such as a tool for the development of the receiver performance analysis, design, and analysis for the DTV coverage areas, etc. This system can also be used as RF signal analyzer.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.