• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2067-2080
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• 1994

Recently, joint blind equalization and carrier recovery for digital mobile transmission system is of growing interest. In this paper, we describe new receiver structure of joint godard blind equalizer and various recovery loop for QAM modulated signal. After a brief review of Godard blind equalizer and MAP estimation Costas loop, Generalized Costas loop, Leclert loop, Angular form loop, we present two kinds of receiver structures for joint blind equalization and carrier recovery. Using a Monto Carlo simulation technique, we can confirm that two kinds of receiver structures operate very well in the steady state.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.3
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• pp.37-45
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• 1982

This paper is a sequel of the Part I paper[1] on the modified digital Costas loop. In this Part II we analyze the performance of the system in the presence of noise. It is shown that, when the input signal is corrupted by additive white Gaussian noise, the noise process in the loop becomes Rician as a result of the tan-1 (.) function of the phase error detector. Steady state probability density functions of phase errors of the first-and second-order loops have been obtained by solving the Chapman-Kolmogorov equation numerically. Also, the mean and variance of phase error in the steady state have been obtained analytically, and are compared with the results obtained by computer simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.55-56
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• 2017

In this paper, a wideband loop antenna is designed using a CPW feeding method for indoor digital TV applications. The proposed loop antenna consists of a square loop and two circular sectors which connect the loop with central feed points, and the CPW feed line is inserted in the lower circular sector. The CPW feed line is designed to match with the 75 ohm port impedance for DTV applications, and the ground slots are etched in order to improve the impedance matching in the middle frequency region. The optimized antenna is fabricated on FR4 substrate, and the experiment results show that it operates in the frequency band of 463-1,280 MHz for a VSWR < 2, which assures the operation in the DTV band.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.317-319
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• 2003

HILS(Hardware In-the Loop Simulation) is commonly used in the development and testing of embedded systems, when those systems cannot be tested easily, thoroughly, and repeated in their operational environments. HILS can be a useful tool to develop products more quickly and cost effectively and also reduces the possibility of serious defects being discovered after production. During the product development period, Design optimization and hardware/software debugging can be performed using HILS skill. This paper describes a HILS model for the STG(Steam-Turbine Generator) Simulator to prove the performance of the developed Digital Governor. It is developed using software technics which can confirm the responses of a real-time system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1492-1497
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• 2017

In this paper, a design method for a CPW-fed wideband loop antenna for indoor digital TV applications is studied. The proposed loop antenna consists of a square loop and two circular sectors which connect the loop with central feed points, and the CPW feed line is inserted in the lower circular sector. The CPW feed line is designed to match with the 75 ohm port impedance for DTV applications, and the ground slots are etched in order to improve the impedance matching in the middle frequency region. The effects of the gap between the circular sectors and the location and dimension of the ground slots on the input reflection coefficient and gain characteristics are examined to obtain the optimal design parameters. The optimized antenna is fabricated on FR4 substrate, and the experiment results show that it operates in the frequency band of 463-1,280 MHz for a VSWR < 2, which assures the operation in the DTV band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.112-116
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• 1992

In this paper, a fuzzy logic controller(FLC) is designed for the pointing loop of the spin-stabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. The pointing loop of the spin-stabilized platform using FLC has better performance of step responses than a proportional controller in case of same loop hain through the software simulation and the experiment of implemented hardware.