• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.36-43
• /
• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.5
• /
• pp.739-745
• /
• 1993

In mobile communication instruments, realization of the frequency synthesizer with high stabililty in temperature is very important. In order to realize a high stability frequency synthesizer, the oscillator providing for reference frequency must be stabilized in various temperature. In accordance to this requirement, the TCXO using digital method is rrealized in this thesis. The DTCXO consists of temperature sensing part, control part and the VCXO. The frequency stability of the realized DTCXO is 0.94 ppm on average. This is an improved result when compared with the 2.5 ppm of the TCXO using analog method.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.12 no.3
• /
• pp.224-238
• /
• 1987

In the proposed spectrum analyzer, open-loop VCO is replaced with PLL synthesizer incorporating digital frequency synthesizer using modulofunction for measuring precise frequencys. Three different frequency bands and channel spacings are realized by single loop synthesizer through the effective design of the system. The newly designed system with square detection has a good linearity of input range from 10mV to 8.5V, as a result the input sensitivity has been improved up to 500uV. The storage function enables us to analyze not only periodic but also nonperiodic wave-form and zoom-in function expands frequency resolution eight times for the dense spectra.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.2
• /
• pp.333-339
• /
• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.35-46
• /
• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.784-787
• /
• 1999

This paper describes a direct digital frequency synthesizer using the CORDIC algorithm, which can be implemented efficiently for a digital sinusoid synthesis. To optimize the hardware design parameters, we perform numerical analysis of the quantization effects for the CORDIC-based architecture. A pipelined architecture is employed to obtain a high data throughput,. We estimate and summarize its hardware costs for a variable accuracy, and a CORDIC-based architecture for 9 bit accuracy is emulated in FPGA.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.4
• /
• pp.291-297
• /
• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.6
• /
• pp.671-678
• /
• 2014

This paper presents a Ka-band FMCW sensor that has high linearity by improving a nonlinear behavior of the voltage controlled oscillator. Due to the nonlinear characteristics of the voltage controlled oscillator for the conventional method, the drift of beat frequency can cause inaccuracy and errors to the extracted results. A Ka-band FMCW signal with fast transition time could be generated by using both direct digital synthesizer and phase locked loop in this research. The implemented FMCW sensor showed very high accuracy in beat frequency through the test.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.48 no.1
• /
• pp.73-79
• /
• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.8
• /
• pp.809-815
• /
• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.