• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.19-21
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• 1984

A design of digital loaded-line phase shifter circuits with PIN Diode is presented. A computer program showes that any phase difference which is satisfied with the condition of minimun VSWR can be obtained with variable stub length and spacing between stubs. A 30 phase bit is designed and measured at 3Gh. Experimental and theoretical performance are compared and found to be in good agreement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Transactions of the Korean Society of Automotive Engineers
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• v.14 no.5
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• pp.17-24
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• 2006

Anti-lock brake system(ABS) are designed to prevent wheel lock on all wheels of the vehicle by sensing wheel angular speed, processing the speed sensor signals in suitable digital electronic control circuits and comanding electrohydraulic actuators to control brake pressure. This study considers a control of ABS using wheel circumferential acceleration thresholds which avoids dangerous wheel locking due to excessive brake pressure during the vehicle braking and discusses the 3-channels, 3-sensors ABS system that employs "independent control" technique for the front wheels and "select low" technique for the rear wheels. The validities of the ABS such as vehicle stability, steerability and stopping distance during braking are assured through the vehicle tests on uniform asphalt straight roads.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.7
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• pp.1204-1210
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• 2016

The phase currents must be accurately measured to achieve the instantaneous torque control of AC motors. In general, those are measured using the current sensors. However, the measured current signals can include the offset errors and scaling errors by several components such as current sensors, analog amplifiers, noise filter circuits, and analog-to-digital converters. Therefore, the torque-controlled performance can be deteriorated by the current measurement errors. In this paper we have analyzed the influence caused by vector control of 2-phase induction motor when two errors are included in measured phase currents. Based on analyzed results, the compensation method is proposed without additional hardware. The proposed compensation method was applied vector-controlled inverter for 2-phase induction motor of 360[W] class and verified through computer simulations and experiments.

• Journal of Advanced Navigation Technology
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• v.17 no.3
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• pp.292-297
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• 2013

In this paper, The design of digital circuits for chaotic composition function which is used for the key-stream generator is studied in this work. The overall design concept and procedure due to the mathematical model of chaotic key-stream generator is to be the explained in detail, and also the discretized truth table of chaotic composition function is presented in this paper. consequently, a composition state machine based on the compositive map with connecting two types of one dimensional and two dimensional chaotic maps together is designed and presented.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1449-1457
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• 2019

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.05a
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• pp.515-520
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• 1996

Since the conventional Westinghouse DNB (Departure from Nucleate Boiling) protection logic is implemented on analog circuits, the logic must be very simple. However, if the DNB protection logic is implemented in a digital processor, a little bit of complexity can be allowed to increase the thermal (or operation) margin. The Westinghouse OTΔT DNB protection logic heavily restricts the operation region by applying the same logic for a full range of pressure in order to maintain its simplicity. In this work, the different DNB protection logic is used for several regions of pressure. The proposed method is applied to Yonggwang 1&2 nuclear power plants and it is calculated that the improved OTΔT can have 5.07% percent more thermal margin than the conventional OTΔT trip logic.