• Transactions of Materials Processing
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• v.16 no.4 s.94
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• pp.313-316
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• 2007

The purpose of this paper is the development of measurement algorithm for green-sheet based on the digital image processing technique. The Low Temperature Co-fired Ceramic(LTCC) technology can be employed to produce multilayer circuits with the help of single tapes, which are used to apply conductive, dielectric and/or resistive pastes on. These single green-sheets must be laminated together and fired at the same time. Main function of the green-sheet film measurement algorithm is to measure the position and size of the punching hole in each single layer. The line scan camera coupled with motorized X-Y stage is used. In order to measure the entire film area using several scanning steps, an overlapping method is used.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.21-24
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• 2018

A temperature sensor with a binary output was implemented using switched-capacitor circuits in a $0.35-{\mu}m$ CMOS(com-plementary metal-oxide semiconductor) process. The measured temperature exhibited good agreement with the oven temperature after calibration. The measured power consumption was 5.61 mW, slightly lower than the simulated power consumption of 6.63 mW.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.92-94
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• 2003

In superconductive digital logic circuits, D2 cells can be used to compose a decoder an important component of an Arithmetic Logic Unit (ALU). In this wor, we simulated D2 cell by using WRspice. D2 cell has one input, one switch input, and two outputs (output1 and output2). D2 cell functions in such way that output1 follows the input and output2 is the complement of the input data, when the switch input is "0, ". However, when there is a switch input "1, " the opposite output signals are generated. In this paper, we optimized a D2 cell by using WRspice, and obtained the minimum margin of 26%. Our optimized D2 cell will play a key role in the ALU fabrication.the ALU fabrication.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Food Science and Preservation
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• v.1 no.2
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• pp.99-105
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• 1994

To convert the analog signal from the drying process into the digital signal, the interface circuit was designed and built. To measure the weight and temperature during drying process, strain gauge type load cell and temperature transducer composed of pt 100 $\Omega$ thermometers and wheatstone bridge circuits were built and used. The temperature control device was composed of photocoupler and triac. Microcomputer aided experimental convective drying system was built with above cricuits and devices. Drying characteristics of onions can be estimated using this system.

• Journal of Magnetics
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• v.14 no.2
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• pp.97-100
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• 2009

A new eddy current testing probe was developed to separate the eddy current signal distortion caused by permeability variation clusters and ordinary defects created in steam generator tubes. Signal processing circuits were inserted into the probe to increase the signal-to-noise ratio and allow digital signal transmission. The new probe could measure and separate the magnetic phases created in the steam generator tubes in the operating environment of a nuclear power plant. Furthermore, the new eddy current testing probe can measure the defects in steam generator tubes as rapidly as a bobbin probe with enhanced testing speed and reliability of defect detection.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1390-1393
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• 2002

Comparative analysis of driving inverters for piezo-electric transformer (PT) is performed and the suit- able drive circuit for portable devices such as personal digital assistants (PDA) is chosen with the experiment in this paper. As a result, a single-switch inverter with a small two winding reactor is chosen, and then the advantages of this method are clarified. It is also confirmed that the driving inverter with this method enables to realize a stabilized AC 400v output and 82% power efficiency from DC 3V input under the conditions of the variations of load current or input voltage from the experiments. Piezo-electric Transformer, Back-Light System, Single-Switch Driving Circuits, Control Method

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.55-60
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• 1984

With the advancement of CMOS technology, it has become attractive to employ complex gate structures in realizing digital circuits. A new test generation algorithm for CMOS complex gates to detect all stuck-open and stuck-on faults considering internal gate response and unknown state is proposed. Minimal and complete set can be derived by this algorithm. Also, it is verified that such a test set is generated applying this algorithm to arbitrary CMOS complex gates by computer.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.661-662
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• 2006

This paper introduces a CMOS clock driver that shows a high efficiency of electric power (lower power consumption) with the supply of lower voltage(VDD), by taking advantage of charge recycling technology. Comparing with the existing structure, this driver showed the improved maximum efficiency of electric power; 72% and 68%, with the supplied voltage of 1.8v and 1.2v, respectively. Since the output waveform shows the tri-state operating region, utilization is expected in the digital integrated circuits.