• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Information and Communications Magazine
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• v.11 no.4
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• pp.62-70
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• 1994

This paper discusses the LAN interface technics physically applicable to the ISDN exchange system through frame relay without changing of the basic exchange architecture. To ensure the success of frame relaying, it's interworking with the existing X.25 services is very imported, and for this purpose both X.75 and 1.122-based interworking alternative must be considered. Definition required to frame relay, interconnection of remote bridge and ways to design the Frame Handler carrying a frame realying in the ISDN node was introduced here. Subsequently, alternatives using the X.25 and X.75 or 1.122 as well as interconnection mechanism LAN and ISDN for the LAN interface and LAN and/or LAN interface and ISDN through frame relay was individually introduced. Through frame relay applications in the major countries, the achievement of high speed frame relaying service to the LAN was introduced.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.4
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• pp.89-101
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• 2006

This paper addresses Electrical Power Subsystem(EPS) design and verification of HAUSAT-2 small satellite through energy balance analysis(EBA) depending on individual operation modes. GaAs solar cells are used for satellite power generation and digital peak power tracking is implemented for EPS architecture. One battery pack is consisted of 4 Li-Ion cells. Battery charge is accomplished by peak power tracker and battery charge regulator. Power conditioning assembly uses three DC-DC converters, and power distribution assembly which consists of commercial IC and MOSFET switch distributes power to subsystems and payloads. The altitude of 650km and sun-synchronous LEO with various local time ascending node(LTAN) are considered in EBA.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.299-300
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• 1998

Recently the development of medical modality like as MRI, 3D US, DR etc is very active. Therefore it is more required not only the enhancement of quality in medical service but the improvement of medical system based on quantization, minimization, and optimization of high speed. Especially, as the changing into the digital modality system, it gets to start using ASIC(Application Specific Integrated Circuit) to realize one board system. It requires the implementation of hardware debugging and effective speedy algorithm with more speed and accuracy in order to support and replace existing device. If objected image could be linked to high speed process board with special interface and pre-processed using FPGA, it can be used in real time image processing and protocol of HIS(Hospital Information System). This study can support the basic circuit design of medical image board which is able to realize image processing basically using digitalized medical image, and to interface between existing device and image board containing image processing algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• Journal of the Korean housing association
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• v.21 no.4
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• pp.89-97
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• 2010

Digital convergence era has been already started and is rapidly developed. Recently, convergency technology became an essential issue in all industries, and is expected to accelerate. This means that we can experience growth and change of architecture using new technology and approaching method. The AR (Augmented Reality) technology, among these convergence technology, is a kind of virtual reality technology that user can see a scene of real world which is overlapped by virtual world with additional information. It has been used in manufacturing and management in the whole industry fields including medical, mechanical, military field and so on because it can provide higher sense of reality. Thus, in this paper, we suggest the utilization of AR technology for organically connecting the roads, facilities, green area, landscape and others in the layout planning of housing complex. Users can see real world with virtual object by overlap computer graphic on the real world. This method provides users with various information about territoriality and openness. As the result of this study it is expected that this technology will help the layout planning of housing complex to become more reasonable in the aspect of design, time and cost.

• Korean Journal of Remote Sensing
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• v.31 no.1
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• pp.1-9
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• 2015

Mobility and cloud platform have become the dominant paradigm to develop web services dealing with huge and diverse digital contents for scientific solution or engineering application. These two trends are technically combined into mobile cloud computing environment taking beneficial points from each. The intention of this study is to design and implement a mobile cloud application for remotely sensed image fusion for the further practical geo-based mobile services. In this implementation, the system architecture consists of two parts: mobile web client and cloud application server. Mobile web client is for user interface regarding image fusion application processing and image visualization and for mobile web service of data listing and browsing. Cloud application server works on OpenStack, open source cloud platform. In this part, three server instances are generated as web server instance, tiling server instance, and fusion server instance. With metadata browsing of the processing data, image fusion by Bayesian approach is performed using functions within Orfeo Toolbox (OTB), open source remote sensing library. In addition, similarity of fused images with respect to input image set is estimated by histogram distance metrics. This result can be used as the reference criterion for user parameter choice on Bayesian image fusion. It is thought that the implementation strategy for mobile cloud application based on full open sources provides good points for a mobile service supporting specific remote sensing functions, besides image fusion schemes, by user demands to expand remote sensing application fields.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.3
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• pp.197-205
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• 2004

In this paper, we studied on the hardware implementation of a 3${\times}$3 window weighted median filter using bit-level sorting algorithm. The weighted median filter is a generalization of the median filter that is able to preserve :,harp changes in signal and is very effective in removing impulse noise. It has been successfully applied in various areas such as digital signal and video/image processing. The weighted median filters are, for the most part, based on word-level sorting methods, which have more hardware and time complexity, However, the proposed bit-serial sorting algorithm uses weighted adder tree to overcome those disadvantages. It also offers a simple pipelined filter architecture that is highly regular with repeated modules and is very suitable for weighted median filtering. The algorithm was implemented by VHDL and graphical environment in MAX＋PlusII of ALTERA. The simulation results indicate that the proposed design method is more efficient than the traditional ones.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.