• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.13-20
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• 1996

Recently, for implementation of neural networks extensive studies have been done especially VLSI technology has been regarded as the one of the most attractive means to implement neural networks. The main drawbacks of digital VLSI implementations are their large area and slow processing speed. In this paper to solve the speed and size problems we designed the efficient architecture using the binary convolution method for basic operation of neural cell, multiplication and addition. When it is used for implementing 3-layer network with 16 neural cell per layer that used neural cell based on binary convolution, clock of 50MHz and 26MCPS on 0.8${\mu}$ standard cell library has been achieved.

• Journal of Digital Contents Society
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• v.6 no.1
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• pp.1-5
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• 2005

This paper describes the main characteristics of Grid Services based on OGSA and a Grid service for aggregating service data element(SDE)s. In order to build a Grid Service, it needs to consider a systematic building approach from the high-level software architecture that represents the main system components and their interactions. The purpose of this paper is to design and implement an extended service data aggregator service in which SDE is a basic unit for collecting resource information. A GT3 based service data aggregator service is extended to apply the multiple collections based storage scheme for maintaining persistently SDEs with a XML DBMS Xindice. To provide efficient aggregating service for service data elements, which is running under wide area environment like Internet, the aggregator service is asynchronously operated by notification mechanism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.873-892
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• 1998

In this paper, we propose an architecture of multimedia communication terminal that can e used in broadband ISDN environments. To design and implement the multimedia communication terminal, we analyzed the structure of multimedia terminals and the types of services which is recommended by public and private standard or ganization, such as ITU-T, Digital Audio-Visual Council(davic) and ATM Forum. The multifunctional communication terminal designed in this paper could allow inter-working between existing communication terminals on the heterogeneousnetwork and accept current and advanced multimedia communication application flexible. An implemented terminal is consisted of the multimedia processing board and the ATm interface board that is installed in PCI bus on personal computer. The integrated service multimedia communication terminal that is implemented supports retrieval, distributive and conversational communication service simultaneously. And then we performaned functional module test according to the individual communication services.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.4
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• pp.25-31
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• 2015

Smart healthcare environments which merge medical and IT technology are getting ready for the third generation centering EHR from current second generation. As a basic technology for the introduction and activation of EHR systems it requires heterogeneous network interworking techniques between various wired and wireless medical devices. Interworking technology for heterogeneous network among various medical devices is needed to introduce EHR system. The heterogeneous network interworking technology is needed for construction of a reliable data system to convert each of unstructured data into structured data. Therefore, in this paper, we identify the domestic and international trends of smart medical field and analyze the characteristics of wired and wireless communication technology that is used in a heterogeneous network. and also suggest requirements needed for interworking technology and provide interworking technology based on them. we expect that proposed method which is designed for smart healthcare environments would provide a basic architecture needed for third smart medical technology generation.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.312-319
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• 2011

In this paper, a new linearization algorithm for DPD(Digital PreDistorter) is suggested. This new algorithm uses DFP(Davidon-Fletcher-Powell) method. This algorithm is more accurate than that of the existing algorithms, and this method renew the best-fit value in every routine with out setting the initial value of step-size. In modeling power amplifier, the memory polynomial model which can model the memory effect of the power amplifier is used. And the overall structure of linearizer is based on an indirect learning architecture. In order to verify for performance of proposed algorithm, we compared with LMS(Least Mean-Squares), RLS(Recursive Least squares) algorithm.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.3
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• pp.11-22
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• 2012

GIS have expanded the use-range to the various application area with the advantage of interface environment, the various geographical operation. topological analysis by the friendly user. Early GIS software was developed as monolithic tool in which all functions packed in the same software. But, these GIS software have the problems of the high cost of constructing system, closely related system architecture and the reusability. And there is a lack of interoperability between them because most of them have their own unique data format according to their practical application fields. So Component is a unit that it is cohesive software package which is able to be developed and arranged independently and connected with another component for necessary system composition. In this paper, we analyze the requirements for component design and component specifications based on the extracted components. Commonly used to extract components from the requirements of the GPS component-based development process is presented. These components extracted by the process can be used to assemble components only. In particular, applications for developers to add features specific case without affecting the other components that can be modify the component.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.1
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• pp.1-7
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• 2019

The objective of this study is to examine the trends in big data. Research abstracts were extracted from 4,019 articles, published between 1995 and 2018, on Web of Science and were analyzed using topic modeling and time series analysis. The 20 single-term topics that appeared most frequently were as follows: model, technology, algorithm, problem, performance, network, framework, analytics, management, process, value, user, knowledge, dataset, resource, service, cloud, storage, business, and health. The 20 multi-term topics were as follows: sense technology architecture (T10), decision system (T18), classification algorithm (T03), data analytics (T17), system performance (T09), data science (T06), distribution method (T20), service dataset (T19), network communication (T05), customer & business (T16), cloud computing (T02), health care (T14), smart city (T11), patient & disease (T04), privacy & security (T08), research design (T01), social media (T12), student & education (T13), energy consumption (T07), supply chain management (T15). The time series data indicated that the 40 single-term topics and multi-term topics were hot topics. This study provides suggestions for future research.

• Architectural research
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• v.22 no.4
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• pp.155-162
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• 2020

Numerous scholars have explored the modeling, control, and optimization of energy systems in buildings, offering new insights about technology and environments that can advance industry innovation. Eye trackers deliver objective eye-gaze data about visual and attentional processes. Due to its flexibility, accuracy, and efficiency in research, eye tracking has a control scheme that makes measuring rapid eye movement in three-dimensional space possible (e.g., virtual reality, augmented reality). Because eye movement is an effective modality for digital interaction with a virtual environment, tracking how users scan a visual field and fix on various digital objects can help designers optimize building environments and materials. Although several scholars have conducted Virtual Reality studies in three-dimensional space, scholars have not agreed on a consistent way to analyze eye tracking data. We conducted eye tracking experiments using objects in three-dimensional space to find an objective way to process quantitative visual data. By applying a 12 × 12 grid framework for eye tracking analysis, we investigated how people gazed at objects in a virtual space wearing a headmounted display. The findings provide an empirical base for a standardized protocol for analyzing eye tracking data in the context of virtual environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.