• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2008년도 학술대회 1부
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• pp.236-239
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• 2008

본 논문에서는 이동단말기를 이용하는 디지털 TV 인터랙티브 게임을 설계하고 구현하였다 이 프로그램은 시청자로 하여금 이동단말기를 이용하여 게임에 참여하도록 한다. 최근 이동단말기에는 고급 인터페이스가 적용되고 있다. 특히 터치패드 형식의 인터페이스가 각광받고 있다. 터치패드 형식의 인터페이스는 TV 게임유저에게 보다 익숙한 인터페이스를 제공하고 사용자로부터 다양한 형태의 입력을 받을 수 있다는 장점이 있다. 이동단말기를 이용하면 여러 명의 이동단말기 사용자들이 동시에 TV 게임에 참여할 수 있으며, 각 사용자에게 보조 화면을 제공 할 수 있다. 본 논문에서는 제안된 프로그램의 장점을 상세히 기술하고 전체 구조를 설명한다. 그리고 구현된 인터랙티브 게임을 실제 방송환경과 유사한 환경에서 모의 시연한다.

• 정보보호학회논문지
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• 제21권2호
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• pp.71-82
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• 2011

라이브 포렌식은 하드디스크 파일시스템 분석으로 획득할 수 없는 메모리 내의 활성 데이터를 얻을 수 있다는 장점으로 인해 최근의 포렌식 조사 시 활용되고 있다. 하지만 기존의 라이브 포렌식은 활성 시스템에서 시스템 정보를 획득하기 위한 명령어 기반의 도구를 사용함으로써, 악성코드에 의한 변조된 결과 획득 및 재분석이 용이하지 못한 단점을 가지고 있다. 따라서 본 논문은 시스템 조사 도구를 이용한 라이브 포렌식의 단점을 보완하기 위한 윈도우즈커널 객체 구조 설명 및 분석 방법을 설명한다. 또한, 이를 활용하기 위한 도구를 설계 및 구현하였고, 실험 결과를 통해 그 효과를 입증한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권2호
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• pp.486-503
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• 2023

Logs play an important role in mastering the health of the system, experienced operation and maintenance engineer can judge which part of the system has a problem by checking the logs. In recent years, many system architectures have changed from single application to distributed application, which leads to a very huge number of logs in the system and manually check the logs to find system errors impractically. To solve the above problems, we propose a method based on Message Middleware and ATT-GRU (Attention Gate Recurrent Unit) to detect the logs anomaly of distributed systems. The works of this paper mainly include two aspects: (1) We design a high-performance distributed logs collection architecture to complete the logs collection of the distributed system. (2)We improve the existing GRU by introducing the attention mechanism to weight the key parts of the logs sequence, which can improve the training efficiency and recognition accuracy of the model to a certain extent. The results of experiments show that our method has better superiority and reliability.

• 디지털융복합연구
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• 제20권2호
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• pp.277-287
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• 2022

제로에너지 건축물(ZEB)은 건축물 자체의 에너지 자립도를 높인 건축물로서 에너지를 생산할 수 있는 신재생 요소가 필수적이며, 건물형 태양광(BIPV)이 가장 주목받고 있는 기술이다. ZEB의 설계에서 BIPV은 설계 초기에 계획되어야 하나, 초기 단계에서 BIPV 계획은 미비한 실정이다. 이에 본 연구에서는 설계 초기 BIPV의 계획과 ZEB 자립률 검토를 위해, 3차원 설계와 빅데이터의 융·복합 설계기술인 건축물 정보통합 모델링(BIM)을 기반으로, BIM과 ZEB에 대한 이론적 고찰 및 ZEB 자립률 분석을 위한 요소를 도출하고, BIPV 에너지 생산량과 건물 에너지 소비량 산출 방법을 분석하였다. 최종적으로, 프로젝트 모델에서 에너지 자립률을 산정하고, 등급 기준을 검토함으로써, 설계 초기 ZEB의 에너지 자립률 산정에 대한 기초적인 연구 방법을 제시하였다. 이를 통해, ZEB 주체자의 의사결정을 지원함으로써 설계 생산성을 향상시킬 수 있을 것으로 기대된다.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.222-226
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• 2009

The objective of this study is to share multimedia contents included in existing digital devices and to solve the problems of an increase in installation fees and non-environmentally friendly interiors. This study designed a new digital signal transmitter and receiver using power line transmission and HDMI in order to solve the problems in the existing systems. The transmitter and receiver designed in this study used an AD9867BCPZ PLC chip in which the transmission came from digital signals originating in a PC, and the system architecture was configured so that the outputs signals were connected to a TV from the receiver. The experiment was implemented by adding a Video Test Generator, a USBPre external sound card, and Smaart Live 6 for analyzing the characteristics of the configured system. In the video test results, it was verified that communication was actively implemented, and the image quality showed a constant level from the measurement of the captured video. In the case of the sound, it was verified that more than 90% of the sound signals were normally transmitted and received from the examination of their phases and magnitudes. Thus, the performance of the system designed in this study was verified, which leads to the resolution of some of the problems found in current digital devices.

• 전자공학회논문지A
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• 제31A권10호
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• 한국태양에너지학회 논문집
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• 제27권4호
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• pp.147-155
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• 2007

It is essential to investigate the structure and the main characteristic of Home USN (Ubiquitous Sensor Network) technologies in built ubiquitous environment while designing future residential space. For this study, three different housing types have been selected to implement ubiquitous technologies for residential space; those are regular, elderly, and single residence units. It is certain that efficiency of ubiquitous home design is improved if main components of each specific housing type are analyzed precisely in digital way and design models are prepared accordingly. Ubiquitous technology, in conclusion, has to be applied not on)r with systematical mechanism or electronic setting but in human-centered atmosphere as well, keeping with deep consideration for bio-housing service factors in eco-friendly surrounding; we call this Ubiquitous Humanism.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.914-918
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• 2000

In this paper, a next generation high speed QPSK transmitter is designed based on 1.8${\mu}$m design rule. The designed transmitter supports the MPEG2-TS coded packed data for the DAVIC standard. Transmitter is composed of the convolutional coder, the shortened Reed-Solomon coder, and QPSK modulator. The coded packets are modulated in APSK with an RC filter. Especially, Galois Field multiplier with a standard basis is designed with the pipelined parallel architecture. Also, in the QPSK modulator, the RC filter and mixer are simplified into the ROM table, which can improve the performance of the transmitter. The total number of gates for the implemented baseband transmitter is 26,875.