• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.131-141
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• 1998

Video data occurred in multimedia documents consist of a large scale of irregular data including audio-visual, spatial-temporal, and semantic information. In general, it is difficult to grasp the exact meaning of such a video information because video data apparently consist of unmeaningful symbols and numerics. In order to relieve these difficulties, it is necessary to develop an integrated manager for complex structures of video data and provide users of video digital libraries with easy, systematic access mechanisms to video informations. This paper proposes a generic integrated video information model(GIVIM) based on an extended Dublin Core metadata system to effectively store and retrieve video documents in digital libraries. The GIVIM is an integrated mo이 of a video metadata model(VMN) and a video architecture information model(VAIM). We also present design and implementation results of a video document management system(VDMS) based on the GIVIM.

• Convergence Security Journal
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• v.10 no.3
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• pp.9-14
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• 2010

The network architecture and analysis model for evaluating the information security are presented to distribute the reliable and secure multimedia digital contents. Using the firewall and IDS, the function of the proposed model includes the security range, related data collection/analysis, level evaluation and strategy proposal. To develop efficient automatic analysis tool, the inter-distribution algorithm and network design based on the traffic analysis between web-server and user are needed. Furthermore, the efficient algorithm and design of DRM/PKI also should be presented before the development of the automatic information security model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• ETRI Journal
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• v.29 no.3
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• pp.408-410
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• 2007

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.

• Proceedings of the KAIS Fall Conference
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• 2007.05a
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• pp.147-149
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• 2007

"Dynamic Neural Unit"(DNU) based upon the topology of a reverberating circuit in a neuronal pool of the central nervous system. In this thesis, we present a genetic DNU-control scheme for unknown nonlinear systems. Our methodis different from those using supervised learning algorithms, such as the backpropagation (BP) algorithm, that needs training information in each step. The contributions of this thesis are the new approach to constructing neural network architecture and its trainin.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.986-989
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• 1987

This paper describes the basic design concepts and architecture of the subscriber line test feature for the TDX-1A digital switching system. Also, implemented software structure for maintaining the multiprocessor control system employed in TDX-1A, which includes terminal server, MML, test, fault recognition and test result handling.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.454-457
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• 2009

The intent of this paper is to describe a neural network structure called multi dynamic neural network(MDNN), and examine how it can be used in developing a learning scheme for computing robot inverse kinematic transformations. The architecture and learning algorithm of the proposed dynamic neural network structure, the MDNN, are described. Computer simulations are demonstrate the effectiveness of the proposed learning using the MDNN.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.214-214
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• 2004

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.