• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.35 no.7
• /
• pp.296-303
• /
• 1986

The active filter of current injection type is the device which eliminates the harmonics in ac line by injecting the harmonic compensating current into the ac side. And its harmonic reduction performance is entirely dependent on the control scheme of the current-fed inverter and the harmonic compensating current becomes the PWM wave by the inverter. This PWM compensating current can be determined by selecting the switching function properly which eliminates the harmonics up to any order with using no independent sources. The new injection current model is derived by the proposed method which is called the optimized injection method. The overall characteristics of the proposed method are investigated through digital computation and the feasibility is proved with experimental results obtained from the Z-80 microcomputer control of the active filter.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.52-55
• /
• 1996

In order to establish the robust current controller design technique of series wound motor driver system. This paper proposes a method of compensated Bang-Bang current control using a series wound motor driver system under improperly variable load. To get minimum time torque control. A compensated Bang-Bang current controller structure is simpler than the structure of PID plus Bang-Bang controller. This paper shows that a general 8 bits microprocessor be used efficiently implementing such an algorithm. The calculation time of software is extremely small when compared with conventional PID plus Bang-Bang a controller. Both nonlinear operating characteristics of Digital switching elements and Describing Function methods are used for the analysis and synthesis. Real time implementation of compensated Bang-Bang current is achieved. Concept design strategy of the control and PWM waveform generation algorithms are presented in the paper.

• ETRI Journal
• /
• v.5 no.2
• /
• pp.3-8
• /
• 1983

This paper derives the Markov model to calculate the reliability of the Digital Switching System being developed by KETRI. Using the failure states extracted from the system in the course of the modelling, we calculated the reliability of both the service grade and the function of the system. Especially, by including the repair rate into the model, we took optimum advantage of theMarkov process and solved the difficulties in the calculation by reducing the number of states of the system.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.28 no.3
• /
• pp.274-285
• /
• 1992

Among various Power converters, a variable voltage variable frequency (VVVF) three-phase PWM inverter is regarded as most promising power converter due to its capabilities, which permits the control of voltage, frequency and harmonic contents in a single power stage employing only on DC source. As a modulating technique of the PWM inverter, the regular sampling technique has rendered possible the on-line computation and generation of PWM control waveforms with a reasonably high switching frequencies. In this paper, microprocessor based three-phase regular samping PWM inverter with real-time control algorithm and control circuits for driving three phase AC motor has been developed. Harmocic components of PWM waveform were analized theoretically in terms of Bessel function series and then calculated by digital computer and observed with spectrum analyzer.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.5
• /
• pp.1697-1708
• /
• 2017

This paper proposes an algorithm for the differential protection of an Indirect Symmetrical Phase Shift Transformer (ISPST) by considering the different behaviors of the compensated differential current under internal fault and magnetizing inrush conditions. In this algorithm, a criterion function is defined which is based on the difference of amplitude of the wavelet transformation over a specific frequency band. The function has been used for the discrimination between three phase magnetizing inrush and internal fault condition and requires less than a quarter cycle after disturbance. This method is independent of any coefficient or threshold values of wavelet transformation. The merit of this algorithm is demonstrated by the simulation of different faults in series and excitation unit and magnetizing inrush with varying switching conditions on ISPST using PSCAD/EMTDC. Due to unavailability of in-field large interconnected transformers for such a large number of destructive tests, the results are further verified by Real Time Digital Simulator (RSCAD/RTDS). The proposed algorithm has been compared with the conventional harmonic restraint based method that justifies the application of wavelet transform for differential protection of ISPST. The proposed algorithm has also been verified for different rating of ISPSTs and satisfactory results were obtained.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.6
• /
• pp.613-624
• /
• 2011

An MMIC multi-function chip for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. A digital serial-to-parallel converter is included in this chip in order to reduce the number of the control interface. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a relative compact size of 24 $mm^2$(6 mm${\times}$4 mm) exhibits a transmit/receive gain of 24/15 dB and a P1dB of 21 dBm from 8.5 GHz to 10.5 GHz. The RMS errors for the 64 states of the 6-bit phase shift and attenuation were measured to $7^{\circ}$ and 0.3 dB, respectively over the frequency.

• Proceedings of the KIEE Conference
• /
• 2001.11b
• /
• pp.216-218
• /
• 2001

The transformer role is very important in power system operation and control; also its price is very expensive. Therefore many kinds of the efforts for transformer protection have been executed. So for as, current differential relay(87) has been mainly used for transformer protection. But current differential relaying method has several troubles as followings. Differential current can be occurred by transformers inrush current between winding1 and winding2 of transformer when transformer is initially energized. Also harmonic restrained element used in current differential relaying method is one of the causes of relays mal-operation because recently harmonics in power system gradually increase by power switching devices(SVC, FACTS, DSC, etc). Therefore many kinds of effort have been executed to solve the trouble of current differential relay and one of them is method using ratio of increment of flux linkages(RIFL) of the primary and secondary windings. This paper introduces a novel protective relay for power transformers using RIFL of the primary and secondary windings. Novel protective relay successfully discriminates between transformer internal faults and normal operation conditions including inrush and this paper includes real time test results using RTDS(Real Time Digital Simulator) for novel protective relay. A novel protective relay was designed using the TMS320C32 digital signal processor and consisted of DSP module. A/D converter module, DI/DO module, MMI interface module and LCD display module and developed by Xelpower co., Ltd.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.10
• /
• pp.926-934
• /
• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.13 no.3
• /
• pp.143-149
• /
• 2018

It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.687-688
• /
• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.