• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.6
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• pp.64-73
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• 1997

RPWM(Random Pulse Width Modulation) techniques have been attracting an interest as an excellent reduction method of acoustic noise on the inverter drive system. Using randomly changed switching fre-quency of the inverter, the power spectrum of the electromagnetic acoustic noise can be spread out into the wide-band area. The wide band noise is much more comfortable and less annoying than the narrow-band one. This paper describes an implementationof the triangular carrier frequency modultde RPWM inverter drive system The poweer soedtrum of the noise emittde from the induction motro was measured in the anechoic chamber. The analysis of the sources for the acoustic noise and the effects of the noise reduction are confirmed by the ceasured dpectra of the noise. Real-time RPWM along with the speed control was achieved by high speed DSP(Digital Signal Processor ) TmS320C31, By changing the center frequency and the bandwidth of the carrier, theis real-time RPWM scheme can be used as an efficient switching frequency band acoustic noise reduction method for the inverter system with variant load conditions.

• Journal of IKEEE
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• v.26 no.4
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• pp.671-680
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• 2022

In this paper, A 200kW traction motor driver that covers most of the traction motor specification of commercial electric vehicles (EV) is developed. In order to achieve high efficiency and high power density, a next-generation power semiconductors (Silicon carbide, SiC) are applied instead of power semiconductor(IGBT), which is Si based. Through hardware analysis for optimal use of SiC, expected efficiency and heat dissipation characteristics are obtained. A vector control algorithm for an IPMSM (Interior permanent magnet synchronous motor), which is mostly used in EV(Electric vehicle) traction motor, is implemented using DSP (Digital signal processor). In this paper, a prototype traction motor driver based SiC for EV is designed and manufactured, and its performance is verified through experiments.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.4
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• pp.109-119
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• 1999

Switched Reluctance Motor(SRM) have been expanding gradually their awlications in the variable speed drives due to their relatively low cost, simple and robust structure, controllability and high efficiency. In this paper neural network theory is used to detemrine fuzzy-neural network controller's membership ftmctions and fuzzy rules. In addition neural network emulator is used to emulate forward dynamics of SRM and to get error signal at fuzzy-neural controller output layer. Error signal is backpropagated through neural network emulator. The backpropagated error of emulator offers the path which reforms the fuzzy-neural network controller's mmbership ftmctions and fuzzy rules. 32bit Digital Signal Processor(TMS320C31) was used to achieve the high speed control and to realize the fuzzy-neural control algorithm. Simulation and experimental results show that in the case of load variation the proposed control rrethcd was superior to a conventional rrethod in the respect of speed response.sponse.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.959-962
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• 2005

Servomotors are used as key components of automated system by performing accurate positioning, accurate speed regulation, and precise motion control in response to commands from computers and sensors. Especially linear brushless servomotors have numerous advantages over ball screws, timing belts, rack/pinion drives and friction drives compared with rotary servomotors. This paper proposes the estimation of unknown parameters from the linear brushless DC motor which is operated by sinusoidal commutation. The estimated parameters are used to tune the controller gain and disturbance observer. In order to agree with this purpose, Digital Signal Processor(TMS320F240), developed for implementation of a speed Field Oriented Control(FOC), adopted in this study. The processor playing an important role in controller has A/D converters, PWM generators, riched I/O port internally.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1527-1539
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• 2015

In this paper the hardware implementation of the direct torque control based on the fuzzy logic technique of induction motor on the Field-Programmable Gate Array (FPGA) is presented. Due to its complexity, the fuzzy logic technique implemented on a digital system like the DSP (Digital Signal Processor) and microcontroller is characterized by a calculating delay. This delay is due to the processing speed which depends on the system complexity. The limitation of these solutions is inevitable. To solve this problem, an alternative digital solution is used, based on the FPGA, which is characterized by a fast processing speed, to take the advantage of the performances of the fuzzy logic technique in spite of its complex computation. The Conventional Direct Torque Control (CDTC) of the induction machine faces problems, like the high stator flux, electromagnetic torque ripples, and stator current distortions. To overcome the CDTC problems many methods are used such as the space vector modulation which is sensitive to the parameters variations of the machine, the increase in the switches inverter number which increases the cost of the inverter, and the artificial intelligence. In this paper an intelligent technique based on the fuzzy logic is used because it is allows controlling the systems without knowing the mathematical model. Also, we use a new method based on the Xilinx system generator for the hardware implementation of Direct Torque Fuzzy Control (DTFC) on the FPGA. The simulation results of the DTFC are compared to those of the CDTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC and show the Xilinx Virtex V FPGA performances in terms of execution time.

• Proceedings of the KIEE Conference
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• 2001.11b
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• pp.216-218
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• 2001

The transformer role is very important in power system operation and control; also its price is very expensive. Therefore many kinds of the efforts for transformer protection have been executed. So for as, current differential relay(87) has been mainly used for transformer protection. But current differential relaying method has several troubles as followings. Differential current can be occurred by transformers inrush current between winding1 and winding2 of transformer when transformer is initially energized. Also harmonic restrained element used in current differential relaying method is one of the causes of relays mal-operation because recently harmonics in power system gradually increase by power switching devices(SVC, FACTS, DSC, etc). Therefore many kinds of effort have been executed to solve the trouble of current differential relay and one of them is method using ratio of increment of flux linkages(RIFL) of the primary and secondary windings. This paper introduces a novel protective relay for power transformers using RIFL of the primary and secondary windings. Novel protective relay successfully discriminates between transformer internal faults and normal operation conditions including inrush and this paper includes real time test results using RTDS(Real Time Digital Simulator) for novel protective relay. A novel protective relay was designed using the TMS320C32 digital signal processor and consisted of DSP module. A/D converter module, DI/DO module, MMI interface module and LCD display module and developed by Xelpower co., Ltd.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.659-666
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• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.