• Title/Summary/Keyword: Digital Signal Processor(DSP)

Search Result 507, Processing Time 0.031 seconds

Real-Time Hardware Simulator for Grid-Tied PMSG Wind Power System

  • Choy, Young-Do;Han, Byung-Moon;Lee, Jun-Young;Jang, Gil-Soo
    • Journal of Electrical Engineering and Technology
    • /
    • v.6 no.3
    • /
    • pp.375-383
    • /
    • 2011
  • This paper describes a real-time hardware simulator for a grid-tied Permanent Magnet Synchronous Generator (PMSG) wind power system, which consists of an anemometer, a data logger, a motor-generator set with vector drive, and a back-to-back power converter with a digital signal processor (DSP) controller. The anemometer measures real wind speed, and the data is sent to the data logger to calculate the turbine torque. The calculated torque is sent to the vector drive for the induction motor after it is scaled down to the rated simulator power. The motor generates the mechanical power for the PMSG, and the generated electrical power is connected to the grid through a back-to-back converter. The generator-side converter in a back-to-back converter operates in current control mode to track the maximum power point at the given wind speed. The grid-side converter operates to control the direct current link voltage and to correct the power factor. The developed simulator can be used to analyze various mechanical and electrical characteristics of a grid-tied PMSG wind power system. It can also be utilized to educate students or engineers on the operation of grid-tied PMSG wind power system.

Monitoring and Control System for Efficient Operating and Management of Photovoltaic Power Generation System (태양광발전시스템의 효율적 운용과 관리를 위한 모니터링 및 제어 시스템)

  • Bin, Jae-Gu;Kang, Feel-Soon;Kim, Cheul-U
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.11 no.3
    • /
    • pp.532-539
    • /
    • 2007
  • Photovoltaic power generation system is one of new renewable energy sources. Such distributed power generation system has important issues for the system management ad operating after its installation. To solve the problem, remote monitoring and control systems can be employed. In this paper, LabVBEW based monitoring and control system is proposed for efficient management and operation of the photovoltaic power generation system. Interface method between monitoring part and DSP controller is given in detail. The proposed system is verified through experiments using a grid-connected photovoltaic power generation system.

Efficient Matrix Multiplication Algorithms and its Application to Development of a High Performance Embedded System (효율적인 행렬 곱 알고리즘 및 이를 활용한 고성능 임베디드 시스템 개발)

  • Kim, Wonsop;Jeon, Wonbo;Gong, Minsik
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.47 no.1
    • /
    • pp.75-80
    • /
    • 2019
  • In the recent aerospace and defence industries, it is required to develop small and low cost embedded systems. Based on a high speed digital signal processor (DSP), this paper first presents the development of an embedded system. To reduce the computation time of the high precision algorithm such as flight control, we also propose two algorithms for matrix multiplication. Validation results show that, compared to the performance using the $2{\times}2$ unit method, the performance of the proposed method 1 is improved, when the size of matrices is small. The proposed method 2 generally outperforms the $2{\times}2$ unit method.

Implementation of Intelligent Fire-Detection Systems Using DSP (DSP를 이용한 지능형 화재검출시스템 구현)

  • Kim, Hyun-tae;Song, Chong-kwan;Park, Jang-sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2009.05a
    • /
    • pp.411-414
    • /
    • 2009
  • Many victims and property damages are caused in fires every year. In this paper, intelligent fire-detection systems with embedded fire-detection algorithms for early fire detection and alarm is proposed to reduce fire damages by using image processing technique, high speed digital signal processor(DSP) technique, and information technique. The fire detection algorithms used for the proposed systems consist of flame and smoke detection algorithms. If flame or smoke is detected respectively, the corresponding alarm signal can be transferred to management computer. And if flame and smoke is detected simultaneously, the fire alarm signal shall be generated. Through several experiments in the physical environment, it is shown that the proposed system works well without malfunction.

  • PDF

Implementation of a General Purpose DSP board using the ADSP-2105 Digital Signal Processor and its application to a real-time FFT analyzer (ADSP-2105를 이용한 범용 DSP 보드의 제작 및 이를 이용한 실시간 FFT 분석기의 구현)

  • 조철희
    • Proceedings of the Acoustical Society of Korea Conference
    • /
    • 1994.06c
    • /
    • pp.61-64
    • /
    • 1994
  • 디지털 신호를 처리하기 위해 특별히 제작된 ADSP-2105는 빠른 Fied-point 연산과 Harvard-architecture로 구조화됐기 때문에 빠른 수행연산을 할 수 가 있다. 본 논문은 이 DSP 프로세서를 이용해 음성신호의 실시간 FFT 분석에 관한 방법을 소개한다. 실시간 FFT 분석기로서의 DSP 보드는 크게 음성신호를 받는 입력부분과 FFT를 계산하는 FFT 부분으로 나뉘어지는데, 입력부분은 AD1849로 8KHz로 데이터를 샘플링해 받게 되었고, FFT 부분은 실제로 DSP가 FFT를 수행하는 부분으로 되어있다. 실시간 처리를 구현하기 위해 입력 부분은 두 개의 뱅크로 만들어 한 뱅크에서 음성신호를 받아들이는 동안에 다른 뱅크에서는 FFT를 계산하도록 되어있어서 DSP 보드는 항시 음성신호를 샘플링 할 수 있는 상태를 유지할 수 있다. 그리고 FFT 처리부는 빠른 처리로 음성신호를 샘츨링할 뱅크가 채워지기 전에 실행되게 프로그램되어 있어 실제적으로 모든 음성데이타를 FFT 하게 되어있다.

  • PDF

A General Purpose DSP based Multimedia Streaming System (General Purpose DSP 기반의 멀티미디어 스트리밍 시스템 구현)

  • Kim, Dong-Hwan;Moon, Jae-Pil;Oh, Hwa-Yong;Lee, Eun-Seo;Chang, Tae-Gyu
    • Proceedings of the KIEE Conference
    • /
    • 2005.07d
    • /
    • pp.2882-2884
    • /
    • 2005
  • 본 논문에서는 인터넷을 통한 멀티미디어 스트리밍 서비스 환경에서 다양한 표준으로 압축된 컨텐츠의 디코딩을 지원하기 위하여 general purpose DSP (Digital Signal Processor) 기반의 멀티미디어 서비스 플랫폼을 구현하였다. 다양한 표준 방식으로 압축된 멀티미디어 컨텐츠를 재생하기 위하여 Host 프로세서와 DSP 구조의 하드웨어를 설계하고, 멀티미디어 코덱을 DSP에 다운로드하는 소프트웨어적인 기법을 적용하였다. 설계한 플랫폼의 동작을 검증하기 위하여 리눅스 기반에서 DSP를 제어하는 네트워크 클라이언트 소프트웨어를 구현하고, Tl의 TMS 320C6416을 대상으로 구현한 MPEG-2 비디오와 AC-3 오디오 코덱을 적용하여 스트리밍 환경에서 멀티미디어 데이터가 원활하게 재생되는 것을 보였다.

  • PDF

An Implementation Method of Cycle Accurate Simulator for the Design of a Pipelined DSP

  • Park, Hyeong-Bae;Park, Ju-Sung;Kim, Tae-Hoon;Chi, Hua-Jun
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.6 no.4
    • /
    • pp.246-251
    • /
    • 2006
  • In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

Algorithm and Design of Double-base Log Encoder for Flash A/D Converters

  • Son, Nguyen-Minh;Kim, In-Soo;Choi, Jae-Ha;Kim, Jong-Soo
    • Journal of the Institute of Convergence Signal Processing
    • /
    • v.10 no.4
    • /
    • pp.289-293
    • /
    • 2009
  • This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

  • PDF

Performance Enhancement of Underwater Acoustic Communication System Using Hydrophone Transmit Array (하이드로폰 송신 어레이를 이용한 수중 음향 통신 시스템의 성능 향상)

  • 이외형;손윤준;김기만
    • The Journal of the Acoustical Society of Korea
    • /
    • v.21 no.7
    • /
    • pp.606-613
    • /
    • 2002
  • In this paper we applied a transmit beamforming technique to the underwater acoustic communication system for high rate data transmission. A prototype transmit system was designed and implemented with the general purpose DSP processor and multiple digital-to-analog converters. The performances of the implemented system were evaluated by the experiment in water tank. In order to simplify the procedure the channel coding and equalizer were omitted. And the simplest OOK (On-Off Keying) technique in digital communication methods was applied. The experimental result shows that the transmission data rate is higher about 3 times in the case of 5 hydrophone transmitting may than 1 hydrophone transmitter at bit error rate 10/sup -2/. We verified that the maximum data rate was 400 bps for speech signal transmission in water tank.

Real-Time Implementation of AMR Speech Codec Using TMS320VC5510 DSP (TMS320VC5510 DSP를 이용한 AMR 음성부호화기의 실시간 구현)

  • Kim, Jun;Bae, Keun-Sung
    • MALSORI
    • /
    • no.65
    • /
    • pp.143-152
    • /
    • 2008
  • This paper focuses on the real time implementation of an adaptive multi-rate (AMR) speech codec, that is a standard speech codec of IMT-2000, using the TMS320VC5510. The series of TMS320VC55x is a 16-bit fixed-point digital signal processor (DSP) having low power consumption for the use of mobile communications by Texas Instruments (TI) corporation. After we analyze the AMR algorithm and source code as well as the structure and I/O of 7MS320VC55x, we carry out optimizing the programs for real time implementation. The implemented AMR speech codec uses 55.2 kbyte for the program memory and 98.3 kbyte for the data memory, and it requires 709,878 clocks, i.e. about 3.5 ms, for processing a frame of 20 ms speech signal.

  • PDF