• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.879-885
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• 2004

This paper describes an adaptive signal processing of digital receiver with digital down convertor(DDC). DDC is composed of numerically controlled oscillator(NCO) and digital low pass filler and the received signal is processed by numerical algorithm. The simulation results of digital receiver using the passband sampling technique are presented and we confirmed that the received low IF signal is converted to zero IF by numerically processed DDC. Direction of arrival(DOA) estimation technique using multiple signal classification(MUSIC) algorithm with high resolution is also discussed. We knew that an accurate resolution of DOA depends on the input sampling numbers and antenna element numbers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.12
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• pp.986-991
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• 2018

In this paper, an A/D conversion module was designed and fabricated to improve the dynamic range of wideband digital receivers. The A/D conversion module for expanding the dynamic range converts signals into a digital signal by branching the input signal into the normal path and the amplification path according to the input signal level. Test results of the fabricated module show that the normal path of the A/D conversion module converts an input level of -57 dBm to -12 dBm into a digital signal, and the amplification path converts an input level of -30 dBm to +12 dBm into a digital signal without distortion. This translates to an input dynamic range characteristic of 69 dB. Moreover, it is confirmed that the constant output characteristic is exhibited at an instantaneous bandwidth of 100 MHz.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.4
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• pp.385-391
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• 2007

A class D digital audio amplifier with small size, low cost, and high quality is positively necessary in the multimedia era. Since the digital audio amplifier is based on the PWM signal processing, it is improper to analyze the principle of signal generation using linear system theories. In this paper, a class D digital audio amplifier based ADSM (Advanced Delta-Sigma Modulation) is considered. We first model the digital audio amplifier and then explain the operation principle using variable structure control algorithm. Moreover, the ripple signal generated by the hysteresis in the comparator has a significant effect on the system performance. Thus, we present a method to find the magnitude and the frequency of the ripple signal using describing function. Finally, simulations and experiments are provided to show the validity of the proposed methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2329-2338
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• 1997

A conventional digital receiver sampled a baseband signal and processed it digitally for demodulation. But now we can sample at sufficiently high speed a wideband signal to take enough discrete data values due to the advent of economic high-speed ADC. With this technical background, a wideband frequency-division-multiplexed signal can be undersampled and channelized in digital domain by DFT analysis filter using the theory of polyphase. In this paper, we propose a new digital receiver which can digitally process the multichannel received signal by sampling at IF band, develop a mathematical theory and algorithm, and analyze the performance by using C-language simulaation. The proposed receiver can demodulate analog and digital FM signals.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Korean Society for Precision Engineering
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• v.11 no.2
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• pp.32-40
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• 1994

In this study by using EMAT(electro magnetic acoustic transducer)the artificial slit is installed on 12B-SUS pipe test piece. By making 4 cycle SH-burst (EMA) incidence to 45 .deg. angle, the signal data of pulse, received from EMAT are translated into digital-signal-processing- method SSP(Split Spectrum Processing) and Deconvolution method. The main conclusions obtained are as follows; (1) the signal data received from EMAT are translated with digital signal proc- essing of SSP-method and Deconvolution-method and this method shows exellent results more than Ultrasonic testing method does; (2) noise can well be removed by SSP with signal data, and resolution and S/N ratio are advanced; (3) when used with Ultrasonic wave general stainless steel has proporties of multiscattering and reflection phenomena, but resolution is progressed by using Deconvolution method;and (4) as addition-averaging-processing mumber is increasing, the resolution and S/N ratio are improved and the satisfactory signal is obtained.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.93-98
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• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.751-755
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• 1997

This paper presents a new scheme of neural network controller to improve to improve the robustuous of robot manipulator using digital signal processors. Digital processors, DSPs, are micro-processors that are particularly developed for fast numerical computations involving sums and products of variables. Digital version of most advanced control algorithms can be defined as sums and producrs of measured variables, thus it can be programmed and executed through DSPs. In addition, DSPs are as fist in computation as most 32-bit micro-processors and yet at a fraction of their prices. These features make DSPs a viable computational tool in digital implementation of sophisticated controllers. During past decade it was proposed the well-established theorys for the adaptive control of linear systems, but there exits relativly little gensral theoral for the adaptive control of nonlinear systems. Perforating of the proposed controller is illustrated. This paper describes a new approach to the design of adaptive controller and implementation of real-time control for assembling robotic manipulator using digital signal processor. Digital signal processors used in implementing real time adaptive control algorithm are TMS320C50 series made in TI'Co..

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.