• 한국군사과학기술학회지
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• 제22권3호
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• pp.332-340
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• 2019

Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 대한전자공학회논문지
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• 제24권1호
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• pp.1-9
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• 1987

In this paper, the acquisition performance of a receiver that utilizes a non-coherent digital correlator is analyzed. In order to analyze the acquisition performance, the probability density function of a receiver output random variable has been derived approximately. Using this function, the acquisition performance of the coarse acquisition code receiver in a global positioning system is analyzed.

• 한국군사과학기술학회지
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• 제12권2호
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• pp.182-190
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• 2009

GPS receivers can be disrupted by intentional or unintentional jamming, then it is unable to receive GPS signals and it is impossible to get the correct navigation results. Anti-jamming schemes using array antennas are being studied well due to high performance of those, and the efforts to apply them to GPS receiver are also being done. A GPS receiver structure for a multiple beam-forming scheme among those schemes has been proposed in this paper, and the performance is also compared with that using a general GPS receiver structure. For a general GPS receiver structure, each satellite signal which is formed by a beam-forming scheme is summed to be processed in a part of digital signal processing. For a proposed GPS receiver structure, however, each satellite signal is respectively processed by a designated channel in a part of digital signal processing. Finally, it is confirmed that the proposed GPS receiver structure is superior to a general GPS receiver structure in a point of the carrier to noise power ratio and the navigation accuracy using a software platform.

• 전자공학회논문지B
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• 제31B권10호
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• pp.21-31
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• 1994

This paper describes the multichannel combined R2MFC/DTMF/CCT reciver which provides a signaling service functions for call processing control in digital switching system. Using the TMS320C25 DSP chip, we have implemented multi-function receriver shich processes 8 channels of R2MFC, DTMF, and CCT signals simultaneously. In order to increase the channel multiplicity of the combined receiver. R2MFC and CCT receiver were employed by discrete Fourier transform(DFT) method using Goertzel algorithm, and DTMFreceiver was employ by infinite impulse reponse(IIR) filtering method using 4KHz subsampling technique. The combined receiver has 4 function modes for each channel such as R2MFC, DTMF, CCT, and Idle modes. The function mode of each channel may be selected at any time by single-chip micro-controller(.mu.C). Hence, the number of channels assigned for each function mode can be adjusted dynamically according to the signaling traffic variations. From the experimental test results using the test-bed, it has been proved that the combined receiver statisfies all receiver satisfies all receiver specifications, and provides good channel multiplicity and performance, Therefore, it may give a great improvement than existing receiver in cost, reliability, availability, and serviceability.

• 한국음향학회지
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• 제5권4호
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• pp.22-26
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• 1986

The following methods have been proposed for implementing R2 multi-frequency receiver digitally: using digital filters, period-counting algorithm, discrete Fourier transform or Goertzel algorithm, and fast Fourier transform.

• Current Optics and Photonics
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• 제1권4호
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• pp.308-314
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• 2017

A particular optical receiver has its own optical receiver modes (ORMs) determined by its optical and electrical filters. Superposing the ORM waveforms at the transmitter, we can generate a new type of optical signals, called ORM signals. After optical detection, they produce pre-specified voltage waveforms accurately, which is advantageous for digital signal processing. Assuming a Gaussian optical receiver, where the optical and electrical filters are Gaussian, we illustrate various phase-shift keying ORM signals using two ORMs by changing their relative phase. We also illustrate multi-level ORM signal patterns using two or more ORMs.

• 한국컴퓨터정보학회논문지
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• 제17권2호
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• pp.113-118
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• 2012

본 연구에서는 IEEE 802.11 OFDM 수신기에 적용하기 위한 DDC(Digital Down Converter) 설계 방법에 대하여 연구하였다. 상용화 칩으로는 구현이 어려운 WiFi 응용서비스의 요구사항을 만족하기 위해서는 적절한 수신기 개발이 필요하다. OFDM 수신기에서 DDC는 AD 컨버터로부터 업 샘플링된 I/Q(Inphase/Quadrature) 신호를 수신하여 decimation을 위한 신호를 만들기 위해 CIC(Cascaded Integrator Comb) 필터블럭을 거쳐 다운 샘플링한 후 다시 이 신호를 보정하기 위한 FIR(Finite Impulse Response) 필터를 거쳐 출력하는 구조이다. 본 연구에서는 WLAN 규격에 적합한 DDC의 구조 및 설계방법 그리고 설계된 결과물의 시뮬레이션 결과에 대하여 분석하였다.

• 한국통신학회논문지
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• 제39A권1호
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• pp.43-49
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• 2014

본 논문은 최근 표준화가 진행 중인 광역 WPAN에서 주파수 옵셋에 강인한 최적화된 다중 비트 기반 디지털 FSK 수신기에 대해서 제안한다. 광역 WPAN FSK 표준에서는 기존보다 짧은 프리앰블을 사용하고 있으며, 통신반경이 늘어남에 따라 엄격한 BER 요구사항을 제시하고 있다. 이러한 요구사항을 만족하기 위해서 본 논문에서는 CFO가 있는 상황에서도 간단하면서 BER 성능을 만족할 수 있는 최적화된 디지털 FSK 수신기를 설계하였다. 시뮬레이션을 통해 광역 WPAN FSK 시스템에서 필요한 비트 수를 결정하고, 짧은 프리앰블을 사용함에도 CFO에 상관없이 요구 BER 성능을 만족시킬 수 있음을 증명하여 제안된 FSK 수신기가 최근 광역 WPAN 응용에 적절함을 보였다.

• 대한전자공학회논문지TC
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• 제40권12호
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• pp.155-160
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• 2003

ADC (Analog-to-Digital Converter) 와 DSP (Digital Signal Processor) 의 성능이 향상됨에 따라 아날로그 방식으로 처리하던 IF(Intermidiate Frequency) 대역의 신호를 디지털 방식으로 처리할 수 있게 되었다. 이를 디지털 라디오 또는 디지털 IF라 하고 이는 SDR (software definied radio) 의 초기단계라 할 수 있다. 디지털 라디오 개념을 수신단에 적용할 경우 오버샘플링에 의한 처리 이득을 얻을 수 있으며, 다중 캐리어방식의 수신단 설계가 가능하다. 디지털 수신기에서는 연산량 이득을 위해 데시메이션이 이루어지며, CIC (Cascaded Integrated Comb) 및 halfbandHalfband 필터 등이 앨리어싱방지 필터로 사용된다. 그런데, CIC 필터는 필연적으로 통과대역 내에서 롤 오프 현상이 발생하며, 이것은 수신단 필터의 통과대역 평탄도를 악화시켜서 수신성능의 저하를 초래한다. FIR 필터를 이용하여 보상해 주어야 한다. 본 논문에서는 W-CDMA 디지털 수신기의 수신성능에 최적인 CIC 롤오프 보상 필터를 설계방법을 제시하고, 설계된 필터가 CIC필터의 롤오프 특성을 보상하여 BER(Bit Error Rate)을 최소화시킴을 컴퓨터 시뮬레이션을 통해 확인하였다. 필터 성능을 검증하였다.