• Title/Summary/Keyword: Digital Logic

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A 10-bit 10-MS/s 0.18-um CMOS Asynchronous SAR ADC with Time-domain Comparator (시간-도메인 비교기를 이용하는 10-bit 10-MS/s 0.18-um CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Hom;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.88-90
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    • 2012
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

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PLD implementation of the N-D digital filter with VHDL (VHDL을 이용한 다차원 디지털 필터의 PLD 구현)

  • Jeong, Jae-Gil
    • The Journal of Engineering Research
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    • v.6 no.1
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    • pp.111-124
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    • 2004
  • The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

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Vulnerability Case Analysis of the High Power Electromagnetic Pulse on Digital Control System (디지털 제어장치의 고출력 전자기펄스에 대한 취약성 사례 분석)

  • Woo, Jeong Min;Ju, Mun-No;Lee, Hong-Sik;Kang, Sung-Man;Choi, Seung-Kyu;Lee, Jae-Bok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.9
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    • pp.698-706
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    • 2017
  • The risk of high power electromagnetic(HPEM) pulse exposure to the devices used in digital control system such as PLC(programmable logic controller) and communication cable is increasing. In this paper, two different frequency ranges HPEMs were exposed to those control systems to assess the each vulnerability. The vulnerability of the EUTs exposed from HPEM were analyzed and compared with a variation of distances and source power. As the EUTs were exposed to higher level of HPEM, the voltage and communication waveform of the control system had shown a distorted response. And the unshielded twisted pair(UTP) cable connected to the EUTs showed operation failures with induced voltage. However, the foiled twisted pair(FTP) cable shielded the connected device efficiently from the HPEM exposure. Therefore, the necessity of the protection measures against the vulnerability of HPEM exposure for the digital control system used in power facilities and industrial site were verified.

e-Leaming Environments for Digital Circuit Experiments

  • Murakoshi, Hideki
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.58-61
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    • 2003
  • This paper proposes e-Learning environments far digital circuit experiment. The e-Learning environments are implemented as a WBT system that includes the circuits monitoring system and the students management system. In the WBT client-server system, the instructor represents the server and students represent clients. The client computers are equipped with a digital circuit training board and connected to the server on the World Wide Web. The training board consists of a Programmable Logic Device (PLD) and measuring instruments. The instructor can reconfigure the PLD with various circuit designs from the server so that students can investigate signals from the training board. The instructor can monitor the progress of the students using Joint Test Action Grouo(JTAG) technology. We implement the WBT system and a courseware fo digital circuits and evaluation the environments.

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Low Power Design of the Neuroprocessor

  • Pandya, A.S.;Agarwal, Ankur;Chae, G.Y.
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.4 no.1
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    • pp.79-83
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    • 2004
  • This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

A Study on the Performance of the Watermarking with Wavelet Transform

  • Kang, Hwan-Il;Park, Hwan-soo
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.1 no.1
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    • pp.24-28
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    • 2001
  • Wavelet transforms are used for implementing digital watermarking methods in the frequency domain. In this paper, we construct the digital watermarking using various wavelet transforms such as the Daubechies transform, Coiflets transform, Symlets transform and the biorthogonal transform, and we compare each digital watermarking method with the others. We investigate the preservation of the watermark after the data compression attack based on the discrete on the discrete cosine transform. We show that the biorthogonal wavelet, denoted by bior3.5, has the best performance among the wavelet types we selected in an experiment.

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Multi-Channel FIR Digital Filter Hardware Implementation using DQSM Algorithm (DQSM 알고리즘을 이용한 다중채널 FIR디지탈 필터의 구성)

  • 임영도;김명기
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.3
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    • pp.217-226
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    • 1986
  • A method on the hardware implementation of the Multi-channel FIR digital filter using Digital Quarter Square Multiplication(DQSM) algorithm is proposed. This paper describes that ROM requirement can be reduced by using the double precision algorithm and the absolute value circuit, and also execution speed can be improved by reducing logic level steps of absolute value circuit. The frequency response of the four channel FIR digital filter implemented by the above method is quite agreeable with the frequency response simulated by Remez excahange algorithm.

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A Fast A/D Converter using Digital Discriminators (Digital변별기를 이용한 고속A/D변환기)

  • 이병수;이종악
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.7 no.3
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    • pp.125-129
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    • 1982
  • Most A/D converters which encode baseband signals of several magahertz band width to accuracies such as 8 bits are complez and therefore expensive. This letter suggests that a simple fast digital encoder can be formed the combination of V.C.O. and digital discriminator, automatically elimnating the complex logic process of conventional fast baseband A/D converters. The techique is suitable for encoding video signals to 8bits.

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Intelligent Digitally Redesigned Fuzzy Controller

  • Joo, Young-Hoon;Lee, Yeun-Woo;Cha, Dai-Bum;Oh, Jae-Heung
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.2 no.3
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    • pp.220-226
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    • 2002
  • In this paper, we develop the intelligent digitally redesigned fuzzy controller for nonlinear systems. Takagi-Sugeno (TS) fuzzy model is used to model the nonlinear systems and a continuous-time fuzzy-model-based controller is designed based on the extended parallel-distributed-compensation(EPDC) method . The digital controllers are determined from existing analogue controllers. The proposed method provides an accurate and effective method for digital control of continuous-time nonlinear systems and enables us to efficiently implement a digital controller via the pre-determined continuous-time 75 fuzzy-model-based controller. We have applied the proposed method to the duffing forced oscillation system to show the effectiveness and feasibility of the proposed method.

Intelligent Digital Controller Using Digital Redesign

  • Joo, Young-Hoon
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.3 no.2
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    • pp.187-193
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    • 2003
  • In this paper, a systematic design method of the intelligent PAM fuzzy controller for nonlinear systems using the efficient tools-Linear Matrix Inequality and the intelligent digital redesign is proposed. In order to digitally control the nonlinear systems, the TS fuzzy model is used for fuzzy modeling of the given nonlinear system. The convex representation technique also can be utilized for obtaining TS fuzzy models. First, the analog fuzzy-model-based controller is designed such that the closed-loop system is globally asymptotically stable in the sense of Lyapunov stability criterion. The simulation results strongly convince us that the proposed method has great potential in the application to the industry.