• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.571-573
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• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• ETRI Journal
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• 제26권5호
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• pp.501-504
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• 2004

This paper presents a simple gain/phase blind compensation algorithm with an automatic gain control (AGC) function for the adoption of the AGC function and compensation for gain/phase imbalances in quadrature phase shift keying (QPSK) direct conversion receivers (DCRs). The AGC function is interactively operated with the compensation algorithm for gain/phase imbalances. By detecting the gain sum and difference values between the I-channel and Q-channel, the combined AGC and gain imbalance compensation algorithm provides a simpler DCR architecture.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.75-76
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• 2007

이 논문에서는 IS-95와 WCDMA의 Multi-mode로 동작하는 Multi-mode용 저전력 DDC filter 구조를 제안한다. 기존의 DDC구조의 경우 CIC의 통과대역 특성을 향상시켜 주지만, 저지대역의 감쇠특성은 오히려 나빠지는 문제점을 안고 있었다. 제안된 구조는 CIC 데시메이션 필터의 통과대역 특성은 더욱 향상시켜주며, 저지대역의 감쇠특성도 같이 향상시키는 특징을 가진다. 또한 제안된 절터는 각 필터의 면적을 감소시키기 위해 IS-95와 WCDMA의 각각의 모드에 대해 한 개의 필터를 설계한 후 각 모드에 따라 필터 탭 수를 달리하여 동작하는 Multi-mode의 저전력 구조로 구현하였다.

• 한국통신학회논문지
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• 제17권10호
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• pp.1081-1091
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• 1992

전압변환 원리를 이용한 임피던스 변환기의 폿트 종속 디지털 adaptor를 이용하여 임의의 필터규격을 만족하는 웨이브디지탈필터(WDF)를 설계하는 방법을 제안하였다. 기존의 전류변환 원리를 이용한 임피던스 변환기에 의한 WDF의 설계방법은 각종 필터 (LPF, BPF, HPF, BRF)마다 서로 다른 구조로써 실현하여야 한다. 그러나 본 연구에서 제안된 방법은 각종 WDF(LPF, HPF, BPF, BRF)를 한개의 보편적 회로를 이용하여 설계할 수 있음을 밝혔으며 이러한 보편적 회로는 VLSI실현을 위한 회로로써 적합하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.505-508
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• 2001

Currently there is much interested in removing latent charge that is caused to latent image effect and blurring of obtained image as well as reduction of x-ray conversion efficiency in digital radiography system. To remove latent charge a-Se film is irradiated by light with 3500 lux using halogen lamp and optical fiber. We measured dark current and photosensitivity to analyze removing effect of latent charge, then compared with and without light erasing method. The reduction of measured signal due to latent charge effect was 32.3%, and the removal effect of latent charge by using light erase method was its 95.5%.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• 전기학회논문지
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• 제61권1호
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• pp.16-21
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• 2012

The growth in IT industry has brought a corresponding rise in the number of connected digital devices in the distribution network. These digital loads lead to AC to DC conversion losses in order to supply power to them. The more the renewable energies and plug-in electrical vehicles penetrated our lives, the more the electrical losses are caused by AC to DC conversion process. Hence, this paper suggests the methodology for evaluating the amount of power supplied according to the ratio of DC power supply and performs an economic analysis of DC distribution system considering grid parity. In here, the cost of carbon emission reduced by renewable energy is also concerned.

• 한국광학회지
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• 제25권2호
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• pp.85-89
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• 2014

본 논문에서는 광 스캐닝 홀로그래피 기술을 이용하여 실제 반사형 물체의 복소 홀로그램을 스펙클 잡음 없이 촬영하고 데이터양을 줄이면서 동시에 일반적인 진폭 유일 공간 광 변조기를 이용해 광학적인 방법으로 복원할 수 있도록 탈축 수평 시차 홀로그램으로 변환하였다. 변환된 탈축 수평 시차 홀로그램이 공간상에 복원되어 디스플레이가 될 수 있음을 보이기 위하여 수치적인 방법을 이용하여 홀로그램을 복원하였다.

• 인터넷정보학회논문지
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• 제20권1호
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• pp.125-133
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• 2019

Company A should maintain myriad conversion tools for the purpose of making a geometric compilation of navigation maps. Company A is already using complex compilation tools, which are tailored to geographical areas and various GPS models. However, due to frequent requirement and personnel changes, there is an endless challenge for perfect tool configuration and multiple map consolidation. To solve this problem, Company A launched a process automation project using Graphviz, which is an open source workflow graph visualization software. Before implementation, they had to document their current map compilation processes and then match it with the applicable conversion tool. For effective representation of process controls, a new graphical process notation is designed, i.e. Y Block diagram. The authors will compare Y Block diagram with other process notations and explain why Y Block diagram is more useful for tool based business processes such as digital map generation processes.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.