• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.635-638
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• 2009

The latest, Digital art is attempt new field's Art, that is utilize variously digital media image, sound, simulation, 3D holography. A large number of Digital Art is contact with the audiance in pavilion(limit place and limit period). However, It will be possible, If Digital Art can use place digital form media even there are indoor, outdoor, anywhere. This paper analyze reciprocal action for utilize Digital Art in indoor space design, and this paper study expression about indoor design base of interactive.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.39-45
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• 2011

In this paper, the design method of portable signal analysis system is proposed and the hardware module is implemented for operation of base stations based on a common platform for mobile WiMax. The new signal analysis method is implemented as two modules; a broadband RF module and a DSP based digital signal analysis module. The RF module performs the RF-IF down conversion and gain control. And the digital module measure the base staion signal. The differences of performance are insignificant in the experiment results performed through the comparison of other fixed-large system and proposed system.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.103-110
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• 2013

WAVE system is a vehicle communication technology. The system provides the services to prevent vehicle accidents that might occur during driving. Also, it is used to provide various services such as monitoring vehicle management and system failure. In this paper, we divide module that manages WAVE MAC state into a WSMP base MLME module and IP base module and we design and implement a parameter environment between WME module to manage the state of the WAVE system and MLMEX module to mange IP base of WAVE MAC therefore the date to be processed.Also, in order to verify the validity, we have carried out experiments to compare the speed of data processing by dividing data of 5Mbyte, 10Mbyte, 20Mbyte into the packets of 2KByte and 4KByte. Therefore, in WAVE system, the Parameter environments and data processing speed between WME and MLMEX module can be utilized in the various service of vehicle communication technology depending on the speed of data processing.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4291-4310
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• 2015

This paper investigates the traffic offloading over unlicensed bands for two-tier multi-mode small cell networks. We formulate this problem as a Stackelberg game and apply a hierarchical learning framework to jointly maximize the utilities of both macro base station (MBS) and small base stations (SBSs). During the learning process, the MBS behaves as a leader and the SBSs are followers. A pricing mechanism is adopt by MBS and the price information is broadcasted to all SBSs by MBS firstly, then each SBS competes with other SBSs and takes its best response strategies to appropriately allocate the traffic load in licensed and unlicensed band in the sequel, taking the traffic flow payment charged by MBS into consideration. Then, we present a hierarchical Q-learning algorithm (HQL) to discover the Stackelberg equilibrium. Additionally, if some extra information can be obtained via feedback, we propose an improved hierarchical Q-learning algorithm (IHQL) to speed up the SBSs' learning process. Last but not the least, the convergence performance of the proposed two algorithms is analyzed. Numerical experiments are presented to validate the proposed schemes and show the effectiveness.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.3
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• pp.83-95
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• 2022

A technology can be newly formed through technological convergence achieved by the intersection of two or more technological fields. As the complexity of technology development increases, related interest is increasing. Researches have been carried out on the concept, related indicators and analysis of technology convergence including method of social networks. This paper intends to suggest an analysis method of technology convergence using social networks based on the company's possessing technologies. According to the similarity of technologies among companies, a social network was constructed and the technology convergence was analyzed using k-core, a social network subgroup method. Using the result of k-core, base and element technologies for convergence was identified with their relations. Using the suggested method, technology convergence was analyzed on real technology data of defense-industry companies. When the minimum technology similarity is 0, the overall technology convergence relations between technology elements can be identified. In the scope of data in this paper, technologies of defense S/W, aircraft structure and structural materials are identified as important base technology for convergence.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.125-134
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• 2022

Recently, there are an increased the number of reports on the misuse or malicious use of an UAS. Thus, many researchers are studying on defense schemes for UAS by developing or improving C-UAS sensor technology. However, the wrong placement of sensors may lead to a defense failure since the proper placement of sensors is critical for UAS defense. In this study, a multi-object optimization model for C-UAS sensor placement in an air base is proposed. To address the issue, we define two objective functions: the intersection ratio of interested area and the minimum detection range and try to find the optimized placement of sensors that maximizes the two functions. C-UAS placement model is designed using a NSGA-II algorithm, and through experiments and analyses the possibility of its optimization is verified.

• Proceedings of the KIEE Conference
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• 2006.05a
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• pp.78-82
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• 2006

The Partial Discharge Monitoring System is technology which is available to measure & analysis the partial discharge of Power equipment. This technology is in the limelight as a pre-forecast system of equipment defect but there are some problems like no protocol standard, layered network management and the limitation of physical size. This paper presents whole system structure includes engineering centers, LN(Logical Node) to apply PDMS for, base-digital substation system, ICE61850 compatible Condition Monitoring &Diagnosis (CMD), Local Unit(LU), Intelligent Electronic Device (IED) for the solution scheme of these limitations.