• Korean Institute of Interior Design Journal
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• v.22 no.1
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• pp.154-163
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• 2013

This study is aimed to identify the expression and the sense of time in contemporary architectural space. And to classify the system and elements of Zeitlichkeit in the contemporary architectural design. The concept of time can be divided into two meaningful perceptions. Those are the concept of realistic time and the concept of subjective time. These tendencies of theories of architectural space has borrowed from innovations in the sciences, and the whole idea of space-time within art and architecture. Those notions developed through the researches of Bauhaus, Postmodernism, Landscape architecture, Digital Architecture and so forth. The result of this study is that the concepts of time are one of the most important strategies of architectural design and have the various languages which there was not in the past. At the point of the transformation in contemporary architecture, the The concepts of space-time are classified into those from the orders of form and space, from dynamic of the image in the dissolution of architectural form, from traces and steps of movement in dynamic form, and from the systems of commands in the digital softwares. As such, Zeitlichkeit in contemporary architecture means that the architecture moves from the construction of the sensual design elements into Art of life through events and contents which human can experience and recognize. These theories and researches reveal that contemporary architectural movements insert the meaningful stories into architectural space through programs and diagrams.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.405-413
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• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.678-681
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• 2002

In this paper, we propose a block LMS algorithm using distributed arithmetic (BDA) and a multi-memory block structured BDA (MBDA). Moreover, we propose an effective VLSI architecture of adaptive digital filter using MBDA, and evaluate the sampling rate and output latency.

• Journal of The Korean Digital Architecture Interior Association
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• v.4 no.2
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• pp.52-59
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• 2004

The interest about noise and vibration which occurs in buildings is increasing by a living level elevation recently. Particularly, the vibration which occurs from the elevator cage of the building is possibility of damage to the users of the building continuously. So, the purpose of this study is to suggest of measuring results to the vibration that occurs from the elevator cage and propose the countermeasure of it.

• Journal of The Korean Digital Architecture Interior Association
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• v.5 no.2
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• pp.29-35
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• 2005

The interest about noise and vibration which occurs in buildings is increasing by a living level elevation recently. Particularly, the vibration which occurs from the elevator cage of the building is possibility of damage to the users of the building continuously. So, the purpose of this study is a place where it examines closely the vibrating unit of the elevator and propose the countermeasure of it.

• Journal of The Korean Digital Architecture Interior Association
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• v.5 no.2
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• pp.21-28
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• 2005

The main purpose of this paper is to look into the relationship between pavilion and exhibit in Rodin Gallery. Rodin Gallery is intended to accommodate The Gates of Hell and The Burghers of Calais, two materpieces by the French sculptor Auguste Rodin. In order to retain Rodin's intent, the museum designed by KPF is constructed primarily of glass, which maximizes natural light and minimizes shadows. Thematically, the Glass Pavilion was designed to provide a place of relaxation in a highly urban environment.

• ETRI Journal
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• v.29 no.6
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• Journal of The Korean Digital Architecture Interior Association
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• v.2 no.1
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• pp.45-51
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• 2002

The masonry structure has been widely used as the dwelling house structure in our country for a long time. The masonry structure is weak in the lateral forces such as strong wind and earthquake. But there is no regulation for it in the domestic aseismic design codes. The purpose of this study is to suggest a simple design method of un-reinforced masonry wall.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.509-512
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• 2003

On-going convergence between broadcasting and communication is currently bringing in lots of drastic changes to multimedia services to the home. The FTTH-based home networks will be the interface among the digital home appliances for broadcast digital contents as weil as for broadband data connection. In this paper, we discuss several design issues for home gateway architecture that effectively distributes realtime broadcasting contents (from either the headend in the access network or the satellite/terrestrial broadcasts) to heterogeneous devices in the home network.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.157-160
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• 2002

This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.