• Journal of the Korea Academia-Industrial cooperation Society
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• 제10권7호
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• pp.1526-1531
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• 2009

This paper describes the design of a 5th order Elliptic CMOS Gm-C low-voltage filter for the RFID reader IC. The designed filter is composed of CMOS differential transconductors by parallel gain circuits to improve the gain of the conventional self-biased differential amplifier. The filter is designed to operate in low-voltage 1.8V to meet the specification of the RFID reader filter. The results of HSPICE simulation using 1.8V-0.18${\mu}m$CMOS processing parameter showed that the designed 5th order Elliptic low-pass filter satisfied the cutoff frequency of 1.35MHz given by the design specification.

• ETRI Journal
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• 제42권6호
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• The KIPS Transactions:PartA
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• 제11A권2호
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제18권6호
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• pp.863-870
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• 1993

A new methodology of multimedia data composition generated SRT(Synchronization Relation Tree) dynamically after user composing multimedia date by using high level user interface, and processes message passing protocols to adjust multimedia data temporal composition. In this paperl we propose SRT generating algorithm which transfer user defined timeline diagram to SRT dynamically. SRT generating algorithm is to use divide and conquer methodology and recurvise programming. And prove that it generates and type of multimedia date compositon to SRT.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.74-77
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• 2002

In this paper we present a novel temperature compensated Hall effect power IC for accurate operation of wide temperature and high current drive of the motor coil. In order to compensate the temperature dependence of Hall sensitivity with negative temperature coefficient(TC), the differential amplifier has the gain consisted of epi-layer resistor with positive TC. The material of Hall device and epi-resistor is epi-layer with the same mobility. The variation of Hall sensitivity is -38% at 150$^{\circ}C$ and 88% at - 40$^{\circ}C$. But the operating point(B$\sub$op/) and release point(B$\sub$RP/) of the Hall power IC are within ${\pm}$25%. The experimental results show very stable and accurate performance over wide temperature range of -40$^{\circ}C$ to 125$^{\circ}C$.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2733-2736
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• 2003

This paper proposes a dry-type active surface EMG electrode for the myoelectric prosthetic hand. The designed electrode is small size for embedding in the socket of prosthetic hand, and it has three leads including the reference of signal. To acquire EMG signal rejected the power noise, a precision differential amplifier and various filters such as the band pass filter band rejection filter, low pass and high pass filter are embedded on the electrode. The final output of the electrode is integrated absolute EMG (IEMG) obtained by full rectifier and moving average circuits. From experimental results using the implemented dry-type active surface EMG electrode, the proposed electrode is feasible for the myoelectric prosthetic hand.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제28A권12호
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.1944-1947
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• 2005

In this paper, the control of a prosthetic arm using the flex sensor signal is described. The flex sensors are attached to the biceps and triceps brchii muscle. The signals are passed a differential amplifier and noise filter. And then the signals are converted to digital data by PCI 6036E ADC. From the data, position and velocity of arm joint are obtained. Also motion of the forearm - flexion and extension, the pronation and supination are abstracted from the data by proposed algorithm. A two D.O.F arm with RC servo-motor is designed for experiment. The arm length is 200 mm, weight is 4.5 N. The rotation angle of elbow joint is $120^{\circ}$. Also the rotation angle of the wrist is $180^{\circ}$. Through the experiment, we verified the possibility of the prosthetic arm control using the flex sensor signal. We will try to improve the control accuracy of the prosthetic arm continuously.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제19권4호
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• pp.328-333
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• 2006

In this paper, we developed a pressure measurement apparatus with the parallel structure to improve the measurement efficiency of pressure sensors by reducing the measurement time of pressure. The developed system has two parallel positions for loading Silicon pressure sensor and has a dual valve structure. The semiconductor pressure sensors prepared by Copal Electronics were used to confirm the performance of the developed measurement system. Two stage differential amplifier circuit was employed to amplify the weak output signal and the amplified output signal was improved utilizing a low-pass filter. New apparatus shows the measurement time of pressure two times shorter than that of conventional one with the serial structure, while both structures show the similar linear output versus pressure characteristics.

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.606-608
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• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.