• 전자공학회논문지
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• 제50권2호
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• pp.47-53
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• 2013

본 논문에서는 SATA(Serial Advanced Technology Attachment) 커넥터의 차동 임피던스 계산 방법을 적용하여 설계 변경 방법을 제안하고 신호 전달 특성을 개선하였다. 3차원 FEM(Finite Elements Method) 전자기장(Electromagnetic Field) 시뮬레이터를 이용하여 SATA 커넥터의 차동 모드 S-파라미터를 계산하고, 신호 전달 특성을 분석한다. 차동 임피던스는 Odd mode 임피던스를 이용하여 계산되므로 인덕턴스, 커패시턴스, 상호 인덕턴스, 상호 커패시턴스 값이 필요하다. 따라서 시뮬레이터를 이용하여 SATA 커넥터의 각각의 값을 추출하여 차동 임피던스를 계산하였고, 이 값은 $107.3{\Omega}$으로 설계 사양을 만족하지 못하였다. 신호 전달 특성 개선을 위해서 SATA 커넥터의 핀을 $d_x$, $d_y$ 방향으로 설계 변경하고, 각 경우의 신호 전달특성과 차동 임피던스를 분석하였다. $d_y=0.1mm$의 경우에서 신호 전달 특성이 가장 우수하게 나타났고, 차동 임피던스가 $98.7{\Omega}$으로 정합되었다. 이때, 반사손실은 1.5 GHz에서 15 dB 개선되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1977-1978
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• 2008

In this paper, we compare performance of common-mode rejection between a differential and a non-differential amplifier system with two electrodes. A differential amplifier system is constant for common-mode rejection ratio(CMRR) on the frequency domain. But a non-differential amplifier's CMRR is determined by $Z_{FB}/Z_e$ ($Z_{FB}$ ; feedback impedance, $Z_e$; electrode impedance). There is trade-off between a non-differential amplifier's CMRR and its differential input impedance. And a non-differential amplifier system has some advantages for a bio-potential measurement with two electrodes because a designer can control the impedance between the body and system's common.

• 전력전자학회논문지
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• 제26권3호
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• pp.176-182
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• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• ETRI Journal
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• 제35권5호
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• pp.827-837
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• 2013

In this paper, we present wideband common-mode (CM) noise suppression using a vertical stepped impedance electromagnetic bandgap (VSI-EBG) structure for high-speed differential signals in multilayer printed circuit boards. This technique is an original design that enables us to apply the VSI-EBG structure to differential signals without sacrificing the differential characteristics. In addition, the analytical dispersion equations for the bandgap prediction of the CM propagation in the VSIEBG structure are extracted, and the closed-form expressions for the bandgap cutoff frequencies are derived. Based on the dispersion equations, the effects of the impedance ratio, the EBG patch length, and via inductances on the bandgap of the VSI-EBG structure for differential signals are thoroughly examined. The proposed dispersion equations are verified through agreement with the full-wave simulation results. It is experimentally demonstrated that the proposed VSI-EBG structure for differential signaling suppresses the CM noise in the wideband frequency range without degrading the differential characteristics.

• KEPCO Journal on Electric Power and Energy
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• 제6권4호
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• pp.473-480
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• 2020

In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.

• ETRI Journal
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• 제37권3호
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• pp.637-645
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• 2015

Common-mode noise (CMN) is an unresolved problem in wireless capsule endoscopy (WCE) systems. In a WCE system, CMN originates from various electric currents found within the human body or external interference sources and causes critical demodulation performance degradation. The differential operation, a typical method for the removal of CMN rejection, can remove CMN by subtracting two signals simultaneously received by two reception sensors attached to a human body. However, when there is impedance mismatching between the two reception sensors, the differential operation method cannot completely remove CMN. Therefore, to overcome this problem, we propose an enhanced CMN rejection method. The proposed method performs not only subtraction but also addition between two received signals. Then a CMN ratio can be estimated by sufficient accumulation of division operation outcomes between the subtraction and addition outputs during the guard period. Finally, we can reject the residual CMN by combining the subtraction and addition outputs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.289-292
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• 2001

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.470-473
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• 2004

This paper presents conducted emission noise measurement from electronic equipment in frequency range of 1 MHz up to 30 MHz by small loop antenna. Small loop antenna measurement method can measure common-mode (CM) and differential-mode (DM) component of the noise on a pair of power line at the same time. The CM and DM can be measured separately. The theory of this measurement method is introduced and analyzed. The measured results were compared with the conventional measurement by Line Impedance Stabilization Network (LISN) and result a good trend between those methods.

• 한국전자파학회논문지
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• 제27권12호
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• pp.1084-1096
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• 2016

본 논문에서는 12.5 Gbps의 전송 속도를 갖는 고속 직렬 인터페이스 커넥터(high-speed serial interface connector)의 설계 및 분석 방법을 제안한다. 고속 직렬 인터페이스 커넥터는 다양한 매질로 구성되며, 내부 선로도 복잡한 구조를 가지고 있으므로, 선로의 불연속 부분의 각각을 임피던스 정합하기가 매우 어렵다. 따라서 커넥터의 각 부분을 단순화한 커넥터 라인(connector line)의 구조를 제안하였으며, 이 구조에서 R, L, C, G 파라미터를 추출하고 차동 모드 임피던스를 분석하며, TDT(Time Domain Transmissometry)와 TDR(Time Domain Reflectometry)을 이용하여 임피던스 불연속(impedance discontinuity)을 최소화 하는 방법을 제시한다. 본 논문은 단순화한 커넥터 라인에서 추출된 분석 방법 및 결과를 고속 직렬 인터페이스 커넥터에 적용하였다. 제안한 커넥터는 총 44개의 핀(pin)으로 구성되며, 본 논문에서는 4개의 핀의 폭과 간격을 변경하여 신호 전달 특성을 분석하였다. 분석결과, 접지 핀의 폭이 증가할수록 임피던스는 소폭으로 감소하고, 접지핀과 신호 핀 사이의 간격이 증가할수록 임피던스가 증가했다. 또한, 신호 핀의 폭을 증가시키면 임피던스가 감소하며, 신호 핀과 신호 핀 사이의 간격을 늘리면 임피던스가 증가하였다. 최초 커넥터 임피던스 특성은 $96{\sim}139{\Omega}$ 사이에서 변화되는 값을 나타내었으나, 제안된 커넥터 구조를 적용했을 때 임피던스 특성은 $92.6{\sim}107.5{\Omega}$ 사이의 값으로 나타나, 설계 목표 $100{\Omega}{\pm}10%$를 만족함을 보였다.