• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.79-80
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• 2016

본 논문에서는 마이크로스트립 패치의 양측 복사에지로 이중급전되는 안테나의 설계방법에 대해 연구하였다. 안테나로부터 복사된 전자파의 교차편파 레벨이 저감되도록 두 개의 급전선로가 180도 위상차를 갖도록 한다. 제시된 안테나의 동작원리와 설계방법에 대해 등가회로를 이용하여 설명하였다. 제안된 방법의 등가회로로 계산된 반사계수와 상용 안테나 설계 툴을 이용한 시뮬레이션 결과를 비교하여 본 연구의 타당성을 검증하였다.

• 센서학회지
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• 제17권5호
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• pp.387-395
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• 2008

An optic module system is developed adopting multiple colorimetry units for the measurement of multi-pad urinalysis dipsticks. Multiple photometry system instead of moving mechanisms has the advantages of system reliability and simplicity as well as economic aspects due to the recent development of economic color light emitting diodes and stable photo sensors. An integration amplifier with programmable integration time, a current source circuit with selectable and stable current settings were connected through analog multiplexers to thirty light emitting diodes for illumination and ten photo transistors for reading each strip pad. All the circuits are controlled by a microprocessor through a simple set of serial communication commands. The detect ability is eighteen times better than the minimum color difference of the test grading which is 0.013 in urobilinogen in the color space defined in this paper.

• 전기학회논문지
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• 제57권8호
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• pp.1416-1421
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• 2008

A 10 dB branch line hybrid coupler included with defected ground structure (DGS) is proposed. In this contribution, a contact between the grounded metal housing and DGS is avoided, which has been a serious problem in applying DGS to high frequency circuits. An isolation between the metal housing and the DGS pattern is provided by inserting additional substrate between DGS and the metal package. Therefore, it is possible to design branch line hybrid couplers having highly asymmetric power dividing ratio using these DGS structure, which is demonstrated in this paper. The designed and fabricated branch line hybrid coupler using DGS is well packaged in a metal housing without touching the ground metal directly. The measurement is performed under realistic practical operating situations because it is packaged in a metal housing. The measured performances of the fabricated 10dB coupler shows a 1:9 asymmetric power dividing ratio at output ports, as predicted. In addition, the measured performances in terms of matching, isolation, and phase difference are in excellent agreement with the simulated characteristics.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 SMICS 2004 International Symposium on Maritime and Communication Sciences
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• pp.70-73
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• 2004

The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics (Al$_2$O$_3$-SiO$_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a Cu/Al$_2$O$_3$-SiO$_2$ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.308-312
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• 2003

The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics ($Al_2O_3-SiO_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a $Cu/Al_2O_3-SiO_2$ ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권9호
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• 방사선산업학회지
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• 제7권2_3호
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• pp.109-113
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• 2013

In a previous study, a relatively high dose of gamma radiation (1 kGy) did not fully induce typical SOS genes such as sulA, recA, recN, and din in Salmonella Typhimurium (S. Typhimurium) (Lim et al. 2008, Gene expression profiles following high-dose exposure to gamma radiation in Salmonella enterica serovar Typhimuium. J. Radiat. Ind. 3:111-119). In this study, we examined changes in the transcriptional repertoire of S. Typhimurium after a dose of 10 Gy using DNA microarrays. It was found that more than half (~65%) of the 26 up-regulated genes belong to the SOS regulon: ten genes are typical SOS genes, and seven genes are Salmonella prophage genes, which are known to be activated by LexA cleavage. Among 29 down-regulated genes, the function of five genes with the most decreased expression is associated with carbohydrate transport and energy production. This suggests that upon exposure to gamma radiation cells may cease growing by reducing the metabolic activity, and repair DNA damage using a DNA repair system such as the SOS response system. The difference in expression of the SOS genes between a high (1 kGy) and low (10 Gy) dose of radiation shows the possibility that cells may opt for one of multiple regulatory circuits in response to the specific gamma radiation dose.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.151-157
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• 2023

Integrating dielectric materials into LTCC is a convenient method to increase the integration density in electronic circuits. To enable co-firing of the high-k and low-k dielectric LTCC materials in a multi-material hetero-laminate, the shrinkage characteristics of both materials should be similar. Moreover, thermal expansion mismatch between materials during co-firing should be minimized. The alternating stacking of an LTCC with silica filler and that with calcium-zirconate filler was observed to examine the use of the same glass in different LTCCs to minimize the difference in shrinkage and thermal expansion coefficient. For the LTCC of silica filler with a low dielectric constant and that of calcium zirconate filler with a high dielectric constant, the amount of shrinkage was examined through a thermomechanical analysis, and the predicted appropriate fraction of each filler was applied to green sheets by tape casting. The green sheets of different fillers were alternatingly laminated to the thickness of 500 ㎛. As a result of examining the junction, it was observed through SEM that a complete bonding was achieved by constrained sintering in the structure of 'calcium zirconate 50 vol%-silica 30 vol%-calcium zirconate 50 vol%'.

• 전자공학회논문지
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• 제51권5호
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• pp.219-225
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• 2014

본 논문에서는 가정용 교류 전원을 DC 전원으로 변환하여 가전기기에 사용할 수 있는 역률 개선 회로를 설계하였다. 역률은 공급되는 교류 전원의 전압과 전압의 위상차 뿐만 아니라 특정구간에서 발생되는 급격한 전류 파형의 불균형 등과도 관련이 있다. 설계된 본 회로는 부하에 공급되는 교류전력의 전류 파형은 전압파형과 위상차가 적으면서 정현파에 가깝게 공급하는 기능을 제공한다. 자체 발진하는 10[kHz]~100[kHz] 내외의 주파수로 AC 전원에 연결된 코일을 스위칭 한 후 코일전류를 부하에 공급하는 기능을 위한 회로, AC 파형의 zero crossing 지점을 찾는 기능을 함께 수행하는 multiplier 회로, UVLO, OVP, BGR 등의 회로를 한 개의 IC에 집적할 수 있도록 설계하였다. 제작공정은 최소선폭 $0.5[{\mu}m]$, 내압 20[V], 2P_2M CMOS 공정을 사용하여 설계하였고 시뮬레이션을 통하여 전체 기능을 검증하였다.

• 한국과학교육학회지
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• 제14권1호
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• pp.85-102
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• 1994

The purpose of this study was to analyze students' physics problem solving processes and to find the patterns of their problem spaces when high school and university students solved the physics problems. A total of 51 students in a high school and in two universities participated in this study. Their thinking processes in solving 5 physics problems on electric circuit were recorded by using 'thinking aloud' method and were transferal into protocols. 'The protocols were analyzed by the coding system of problem solving process. One of the major theoretical contributions of the computer simulation approach to problem solving is the idea of problem space. Such a concept of problem space was applied to physics problems on electric circuit in this study, and students' protocols were analyzed by the basic problem spaces which were made up from the item analysis by the researcher. The results are as follows: 1) On the average 4.0 test items among 5 ones were solved successfully by all subjects, and all of the items were solved correctly by only 19 persons among all of them. 2) In regard to the general steps of problem solving process, there was little difference for each item between the good solvers and the poor ones. But according to the degree of difficulty of task there was a good deal of difference. For a complex problem all of 4 steps were used by most of students, but for a simple one only 3 steps except evaluating step were used by most of them. 3) It was found in this study that most of students used mainly the microscopic approach, that is, a method of applying Ohm's law on electric circuit simply and immediately, not using the properties of electric circuits. And also it was observed that most of students used the soloing tom below, that is, a solving path in which they were the first to calculate physical Quantities of circuit elements, before they caught hold of the meaning of the given problem regardless of the degree of difficulty.