• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.499-506
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• 2013

The accurate estimation of a fault location is desired in distance protection schemes for transmission lines in order to selectively deactivate a faulted line. However, a typical method to estimate a fault location by calculating impedances with voltages and currents at relaying points may have errors due to various factors such as the mutual impedances of lines, fault impedances, or effects of parallel circuits. The proposed algorithm in this paper begins by extracting the fundamental phasor of the positive sequence currents from the three phase currents. The second-order difference of the phasor is then calculated based on the fundamental phasor of positive sequence currents. The traveling times of the waves generated by a fault are derived from the second-order difference of the phasor. Finally, the distance from the relaying point to the fault is estimated using the traveling times. To analyze the performance of the algorithm, a power system with EHV(Extra High Voltage) untransposed double-circuit transmission lines is modeled and simulated under various fault conditions, such as several fault types, fault locations, and fault inception angles. The results of the simulations show that the proposed algorithm has the capability to estimate the fault locations with high speed and accuracy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.7
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• pp.1240-1246
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• 2000

The finite-difference time-domain (FDTD) method is applied to analyze a single step microstrip discontinuity in the substrate, and an equivalent circuit model comprised of two inductors and a capacitor has been developed using the numerical results. The microstrip discontinuity newly introduced in this paper has a thickness change of the substrate in the longitudinal direction with a uniform strip width. The discontinuity can be applied to the feeding circuit design for the patch antennas and interconnections between microwave circuit modules. The simulation results are compared with those computed by HFSS, and two results showed a good agreement. An equivalent circuit developed from the FDTD results, which is accurate within 2.4% in magnitudes of $S_{11}$ and $S_{21}$,can be applied for the computer-aided design of microwave circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.5
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• pp.486-487
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• 1997

This paper presents the pure capacitive lumped element equivalent circuits for several coplanar waveguide(CPW) discontinuities such as an open-end, an open-end with connected ground planes, a gap and an open-end CPW stub and gives their capacitive element values as a function of physical dimensions of the discontinuity and the frequency for a specific substrate. The capacitive element values are determined from the scattering parameters which are obtained using the finite-difference time-domain(FDTD) method. For an open-end, an open-end with connected ground planes and a gap, the numerical results of the FDTD are compared with the quasi-static results which are calculated using the three- dimensional finite difference method(3D-FDM).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.65-70
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• 2008

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.42-49
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• 2016

In this paper, we design and fabricate an instantaneous frequency measurement receiver with a frequency resolution of 125 MHz which detects and measures continuous signals in 4~6 GHz using path difference of delay lines. The receiver has a 4-bit configuration and consists of power dividers, delay lines, power combiners, power detectors, voltage comparator circuits and so on. The accuracy of the instantaneous frequency measurement is improved by applying offset voltage compensation to the comparator circuits to compensate the frequency-dependent path loss of the delay line and the frequency dependence of power detection.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.477-486
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• 2000

This paper presents Pspice modeling methods for spark gaps and ZnO varistors and describes the application for the two-stage surge suppression circuit which was composed of the nonlinear components. The simulation modelings of nonlinear components were conducted on the basis of the voltage and current curves measured by the impulse current with the time-to-crest of $1~50 \mus$ and the impulse voltage with the rate of the time-to-crest of 10, 100 and 1000 V/\mus$. The firing voltages of the spark gap increased with increasing the rate of the time-to-crest of impulse voltage and the measured data were in good agreement with the simulated data. The I-V curves of the ZnO varistor were measured by applying the impulse currents of which time-to-crests range from 1 to $50 \mus$ and peak amplitudes from 10 A to 2 kA. The simulation modeling was based on the I-V curves replotted by taking away the inductive effects of the test circuit and leads. The meximum difference between the measured and calculated data was of the order of 3%. Also the two-stage surge suppression circuit made of the spark gap and the ZnO varistor was investigated with the impulse voltage of $10/1000\mus$$mutextrm{s}$ wave shape. The overall agreement between the theoretical and experimental results seems to be acceptable. As a consequence, it was known that the proposed simulation techniques could effectively be used to design the surge suppression circuits combined with nonlinear components.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1466-1477
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• 2016

This paper analyzes the electrical characteristic such as the impedance(Z), inductance(L), and cable resistance($R_p$) according to the change of cable length in order to move the electrical sorting device for distinguishing between AF non-insulated track circuits from the center of railway to outside railway. The simulation is performed to check the voltage difference between the voltage of sender and the voltage of receiver and determine the possibility of the voltage restoration availability in the frequency filter band through the capacitor compensation. It was applied to the results of the simulation to the sorting devices installed in the actual field. It is proved the availability by checking the measured voltage characteristic according to the capacitor compensating change of $10{\mu}F$ and $16{\mu}F$ before, and after the length of cable is increased with 6 meters. Through this, the prevention of breakdown and damage to facilities and the prevention the safety-related accidents of line workers from the train are expected according to moving the sorting devices of AR non-insulated track circuits to outside railway.