• Title/Summary/Keyword: Difference Circuits

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Design of a Dual-fed Microstrip Patch Antenna (이중급전 마이크로스트립 패치 안테나 설계)

  • Lee, Jong-Ig;Yeo, Junho;Kim, Gun-kyun;Rhee, Seung-Yeop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.79-80
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    • 2016
  • In this paper, we considered a design method for a microstrip patch antenna fed through two radiating edges by two feeding microstrip lines. Two feedlines are made to have a phase difference of 180 degree with each other in order to reduce cross-polarization level radiated from the antenna. The operation principle and design procedure for the considered antenna are explained using equivalent circuits. In order to check the validity of this study, the results for reflection coefficients of the antenna obtained by the proposed equivalent circuit method and the simulation using commercial antenna design tool are compared with each other.

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Development of multi-colorimeter module for low-cost urinalysis strip readers (저가형 요분석 시스템의 다중 광 검출 모듈개발)

  • Ye, Soo-Young;Jeon, Yong-Uk;Jeong, Do-Un;Jeon, Gye-Rok;Ro, Jung-Hoon
    • Journal of Sensor Science and Technology
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    • v.17 no.5
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    • pp.387-395
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    • 2008
  • An optic module system is developed adopting multiple colorimetry units for the measurement of multi-pad urinalysis dipsticks. Multiple photometry system instead of moving mechanisms has the advantages of system reliability and simplicity as well as economic aspects due to the recent development of economic color light emitting diodes and stable photo sensors. An integration amplifier with programmable integration time, a current source circuit with selectable and stable current settings were connected through analog multiplexers to thirty light emitting diodes for illumination and ten photo transistors for reading each strip pad. All the circuits are controlled by a microprocessor through a simple set of serial communication commands. The detect ability is eighteen times better than the minimum color difference of the test grading which is 0.013 in urobilinogen in the color space defined in this paper.

A New Asymmetric Branch Line Hybrid Coupler without Ground Contact Problem of DGS (접지 접촉 문제가 없는 새로운 DGS 비대칭 브랜치 라인 하이브리드 결합기)

  • Lim, Jong-Sik;Cha, Hyeon-Won;Jeong, Yong-Chae;Park, Ung-Hee;Ahn, Dal
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.8
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    • pp.1416-1421
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    • 2008
  • A 10 dB branch line hybrid coupler included with defected ground structure (DGS) is proposed. In this contribution, a contact between the grounded metal housing and DGS is avoided, which has been a serious problem in applying DGS to high frequency circuits. An isolation between the metal housing and the DGS pattern is provided by inserting additional substrate between DGS and the metal package. Therefore, it is possible to design branch line hybrid couplers having highly asymmetric power dividing ratio using these DGS structure, which is demonstrated in this paper. The designed and fabricated branch line hybrid coupler using DGS is well packaged in a metal housing without touching the ground metal directly. The measurement is performed under realistic practical operating situations because it is packaged in a metal housing. The measured performances of the fabricated 10dB coupler shows a 1:9 asymmetric power dividing ratio at output ports, as predicted. In addition, the measured performances in terms of matching, isolation, and phase difference are in excellent agreement with the simulated characteristics.

Metal/$Al_2O_3-SiO_2$ System Interface Investigations

  • Korobova, N.;Soh, Deawha
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2004.05a
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    • pp.70-73
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    • 2004
  • The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics (Al$_2$O$_3$-SiO$_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a Cu/Al$_2$O$_3$-SiO$_2$ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

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Fracture and Residual Stresses in $Metal/Al_2O_3-SiO_2$ System

  • Soh, D.;Korobova, N.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.308-312
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    • 2003
  • The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics ($Al_2O_3-SiO_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a $Cu/Al_2O_3-SiO_2$ ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

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Related-Key Differential Attacks on CHESS-64

  • Luo, Wei;Guo, Jiansheng
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.9
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    • pp.3266-3285
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    • 2014
  • With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

Induction of SOS Genes by a Low Dose of Gamma Radiation, 10 Gy, in Salmonella enterica Serovar Typhimurium

  • Lim, Sangyong;Joe, Minho;Seo, Hoseong;Kim, Dongho
    • Journal of Radiation Industry
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    • v.7 no.2_3
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    • pp.109-113
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    • 2013
  • In a previous study, a relatively high dose of gamma radiation (1 kGy) did not fully induce typical SOS genes such as sulA, recA, recN, and din in Salmonella Typhimurium (S. Typhimurium) (Lim et al. 2008, Gene expression profiles following high-dose exposure to gamma radiation in Salmonella enterica serovar Typhimuium. J. Radiat. Ind. 3:111-119). In this study, we examined changes in the transcriptional repertoire of S. Typhimurium after a dose of 10 Gy using DNA microarrays. It was found that more than half (~65%) of the 26 up-regulated genes belong to the SOS regulon: ten genes are typical SOS genes, and seven genes are Salmonella prophage genes, which are known to be activated by LexA cleavage. Among 29 down-regulated genes, the function of five genes with the most decreased expression is associated with carbohydrate transport and energy production. This suggests that upon exposure to gamma radiation cells may cease growing by reducing the metabolic activity, and repair DNA damage using a DNA repair system such as the SOS response system. The difference in expression of the SOS genes between a high (1 kGy) and low (10 Gy) dose of radiation shows the possibility that cells may opt for one of multiple regulatory circuits in response to the specific gamma radiation dose.

Suppression of Shrinkage Mismatch in Hetero-Laminates Between Different Functional LTCC Materials

  • Seung Kyu Jeon;Zeehoon Park;Hyo-Soon Shin;Dong-Hun Yeo;Sahn Nahm
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.36 no.2
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    • pp.151-157
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    • 2023
  • Integrating dielectric materials into LTCC is a convenient method to increase the integration density in electronic circuits. To enable co-firing of the high-k and low-k dielectric LTCC materials in a multi-material hetero-laminate, the shrinkage characteristics of both materials should be similar. Moreover, thermal expansion mismatch between materials during co-firing should be minimized. The alternating stacking of an LTCC with silica filler and that with calcium-zirconate filler was observed to examine the use of the same glass in different LTCCs to minimize the difference in shrinkage and thermal expansion coefficient. For the LTCC of silica filler with a low dielectric constant and that of calcium zirconate filler with a high dielectric constant, the amount of shrinkage was examined through a thermomechanical analysis, and the predicted appropriate fraction of each filler was applied to green sheets by tape casting. The green sheets of different fillers were alternatingly laminated to the thickness of 500 ㎛. As a result of examining the junction, it was observed through SEM that a complete bonding was achieved by constrained sintering in the structure of 'calcium zirconate 50 vol%-silica 30 vol%-calcium zirconate 50 vol%'.

An Integrated Circuit design for Power Factor Correction (역률 개선 제어용 집적회로의 설계)

  • Lee, Jun-Sung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.5
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    • pp.219-225
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    • 2014
  • This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.

A Study on Students' Thinking Processes in Solving Physics Problems (물리 문제 해결 과정에서의 학생들의 사고 과정에 관한 연구)

  • Park, Hac-Kyoo;Kwon, Jae-Sool
    • Journal of The Korean Association For Science Education
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    • v.14 no.1
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    • pp.85-102
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    • 1994
  • The purpose of this study was to analyze students' physics problem solving processes and to find the patterns of their problem spaces when high school and university students solved the physics problems. A total of 51 students in a high school and in two universities participated in this study. Their thinking processes in solving 5 physics problems on electric circuit were recorded by using 'thinking aloud' method and were transferal into protocols. 'The protocols were analyzed by the coding system of problem solving process. One of the major theoretical contributions of the computer simulation approach to problem solving is the idea of problem space. Such a concept of problem space was applied to physics problems on electric circuit in this study, and students' protocols were analyzed by the basic problem spaces which were made up from the item analysis by the researcher. The results are as follows: 1) On the average 4.0 test items among 5 ones were solved successfully by all subjects, and all of the items were solved correctly by only 19 persons among all of them. 2) In regard to the general steps of problem solving process, there was little difference for each item between the good solvers and the poor ones. But according to the degree of difficulty of task there was a good deal of difference. For a complex problem all of 4 steps were used by most of students, but for a simple one only 3 steps except evaluating step were used by most of them. 3) It was found in this study that most of students used mainly the microscopic approach, that is, a method of applying Ohm's law on electric circuit simply and immediately, not using the properties of electric circuits. And also it was observed that most of students used the soloing tom below, that is, a solving path in which they were the first to calculate physical Quantities of circuit elements, before they caught hold of the meaning of the given problem regardless of the degree of difficulty.

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