• Electrical & Electronic Materials
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• v.7 no.5
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.225-230
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• 2020

Recently, with the miniaturization of GIS, there is a need for the miniaturization of spacers as accessories. Miniaturized spacers make it difficult to secure adequate insulation distances, resulting in a more concentrated electric field at the triple junction of high-voltage (HV) conductor-insulator (spacer)-insulation gas (SF₆), which is a weakness in GIS. Therefore, by introducing a new concept design technology, functionally graded material (FGM), which is recently applied to various materials and parts industries, three-dimensional control of the dielectric constant distribution in a spacer can be expected to alleviate triple-junction electric field occupancy and improve insulation performance. In this study, we propose an optimized model using NSGA-II to optimize the permittivity distribution of FGM applied spacer.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.293-295
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• 1994

Barium Titanate ($BaTiO_3$) is one of the few titanateds which is cubic at room temperature. It has the perovskite structure, high dielectric constant (${\varepsilon}_r=300$) and a small temperature coefficient of resistance due to it's Low transition temperature ($Tc=120^{\circ}c$). PTCR (Positive Temperature Coefficient of Resistivity) thermistor in thin film $BaTiO_3$ system was prepared by using radio frequency (13.56MHz) and BC magnetron sputter equipment. Polycrystalline, and surface structure characteristics of the specimens were measured by X-ray diffraction (D-Max3, Rigaku, Japan), SEM(Scanning Electron Microscopy: M. JSM84 01, Japan), respectively. Temperature at below $600^{\circ}C$, $1000^{\circ}C$ to $700^{\circ}C$, and above $1100^{\circ}C$ for spotted $BaTiO_3$ thin films showed the amorphous, degree of crystal growth, and polycrystalline, respectively.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.163-168
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• 2017

The aim of the current research was to develop and present an effective methodology for simulating and analyzing the electrical and structural properties of piezoelectric material. The finite element method has been used to make precise numerical models when dielectric, piezoelectric and mechanical properties are known. The static and dynamic responses of circular ring-shaped barium titanate piezoelectric material have been investigated using the commercially available finite element software ABAQUS/CAE. To gain insight into the crystal morphology and to evaluate the purity of the material, a microscopic study was conducted using a scanning electron microscope and energy dispersive x-ray analysis. It is found that the maximum electrical potential of 6.43 V is obtained at a resonance frequency of 35 Hz by increasing the vibrating load. The results were then compared with the experimentally predicted data and the results agreed with each other.

• Transactions on Electrical and Electronic Materials
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• v.13 no.1
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• pp.31-34
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• 2012

The addition of nano/micro silica into unsaturated polyester resin (UPR) results in the improvement of the electrical properties of Silica-UPR composites. The surface, volume resistivity, dielectric strength, dissipation factor and dry arc resistivity of nano silica-UPR composites were found to improve significantly. The effects of the nano and micro fillers in UPR have been evaluated. They are presented in this paper. To evaluate the electrical properties of the nano & micro composites, all the measurements were done as per the prescribed methods in ASTM. It was observed that the addition of nano silica improves the electrical properties as compared to micro silica. The better dispersion of silica particles in unsaturated polyester resin enhances the electrical properties of silica-UPR composites.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.466-468
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• 2009

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.12
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• pp.192-199
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• 2001

Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Laser Solutions
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• v.14 no.4
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• pp.14-20
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• 2011

The advantage of using lasers for through silicon via (TSV) drilling is that they allow higher flexibility during manufacturing because vacuums, lithography, and masks are not required; furthermore, the lasers can be applied to metal and dielectric layers other than silicon. However, conventional nanosecond lasers have disadvantages including that they can cause heat affection around the target area. In contrast, the use of a picosecond laser enables the precise generation of TSVs with a smaller heat affected zone. In this study, a comparison of the thermal and crystallographic defect around laser-drilled holes when using a picosecond laser beam with varing a fluence and repetition rate was conducted. Notably, the higher fluence and repetition rate picosecond laser process increased the experimentally recast layer, surface debris, and dislocation around the hole better than the high fluence and repetition rate. These findings suggest that even the picosecond laser has a heat accumulation effect under high fluence and short pulse interval conditions. To eliminate these defects under the high speed process, the CDE (chemical downstream etching) process was employed and it can prove the possibility to applicate to the TSV industry.

• Journal of Surface Science and Engineering
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• v.32 no.3
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• pp.447-451
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• 1999

Silver has the highest electrical conductivity of all metals and consequently this property is an attractive feature which makes it a leading candidate for use in electronic devices. The research conducted was focused primarily on the development of a process for obtaining a deposited silver-coating onto alumina, for applications related to electrical-conducting devices and, ancillarily, catalysts. Alumina balls and plane substrates were utilized for the investigation. The coating process employed an aqueous ammoniacal silver-nitrate electrolytes with a formaldehyde solution as the reductant. Modifying additives-an activator which would be expected to promote good deposition-characteristics onto the (dielectric) substrate and an inhibitor which would obviate homogeneous reduction (precipitation) of silver was observed when the activator-containing silver-electrolyte reductant constituents were combined. However, the silver-electrolyte/reductant system with inhibitor could be employed (at 8$0^{\circ}C$) to achieve a viable (subject to future research optimization) coating on alumina. The influence of the processing temperature on the deposition process was delineated during the course of the research. The morphology of the deposited-silver on the alumina balls was assessed by SEM imaging. A tape-peel test was employed, with the plane substrates, to semi-quantitatively characterize the adhesion to the alumina.

• Journal of Magnetics
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• v.12 no.1
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• pp.21-26
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• 2007

Si-based electromagnetic noise suppressors on coplanar waveguide transmission lines incorporated with a $SiO_2$ dielectric layer and a nanogranular Co-Fe-Al-O magnetic thin film are reported. Unlike glass-based devices, large signal attenuation is observed even in the bare structure without coating the magnetic thin film. Much larger signal attenuation is achieved in fully integrated devices. The transmission scattering parameter ($S_{21}$) is as small as -90 dB at 20 GHz at the following device dimensions; the thicknesses of the $SiO_2$ and Co-Fe-Al-O thin films are 0.1 $\mu$m and 1 $\mu$m, respectively, the length of the transmission line is 15 mm, and the width of the magnetic thin film is 2000 $\mu$m. In all cases, the reflection scattering parameter ($S_{11}$) is below -10 dB over the whole frequency band. Additional distributed capacitance formed by the Cu transmission line/$SiO_2$/Si substrate is responsible for these characteristics. It is considered that the present noise suppressors based on the Si substrate are a first important step to the realization of MMIC noise suppressors.