• 대한전자공학회논문지SD
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• 제40권5호
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• pp.285-289
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• 2003

본 논문에서는 실리콘 기판상의 전송선로 특성을 개선하기 위하여 표면 마이크로머시닝 기술과 새로운 산화법(H₂O/O₂ 분위기에서 500℃, 1시간 열산화와 1050℃, 2 분간 RTO(Rapid Thermal Oxidation) 공정)을 이용하여 10 ㎛ 두께의 다공질 실리콘 산화막(oxidized porous silicon:OPS) air-bridge 기판 위에 공면 전송선로(Coplanar Waveguide:CPW)를 제작하였다. 간격이 40 ㎛ 신호선이 20 ㎛ 전송선 길이가 2.2 mm인 CPW air-bridge 전송선의 삽입손실은 4 GH에서 -0.28 dB이며, 반사손실은 -22.3 유를 나타내었다. OPS air-bridge 위에 형성된 CPW의 손실이 OPS층 위에 형성된 CPW의 삽입손실보다 약 1 dB 정도 적은 것을 보여주었으며, 반사손실은 35 GHz 범위에서 약 -20 dB를 넘지 않고 있다. 이와 같은 결과로부터 두꺼운 다공질 실리콘 멤브레인 및 air-bridge 구조는 고 저항 실리콘 집적회로 공정에서 고성능, 저가의 마이크로파 및 밀리미터파 회로 응용에 충분히 활용 될 수 있으리라 기대된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 센서학회지
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• 제11권3호
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• pp.163-170
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• 2002

본 논문에서는 양극반응과 복합 산화법($H_2O/O_2$ 분위기에서 $500^{\circ}C$, 1시간 열산화와 $1050^{\circ}C$, 2분간 RTO(Rapid Thermal Oxidation) 공정)을 이용한 두꺼운 OPSL(Oxidized Porous Silicon Layer)을 형성하여 이를 마이크로머시닝 기술을 이용함으로써 $10\;{\mu}m$ 두께의 OPS(Oxidized Porous Silicon) 에어 브리지를 제조하고, 그 위에 전송선로를 형성하여 그 RF 특성을 조사하였다. OPS 에어 브리지 위에 형성된 CPW(Coplanar Waveguide)의 손실이 OPSL 위에 형성된 전송선의 삽입손실보다 약 2dB 정도 적은 것을 보여주었으며, 반사손실은 OPSL 위에 형성된 전송선의 반사손실보다 적으며 약 -20 dB를 넘지 않고 있다. 본 연구에서 개발한 산화된 다공질 실리콘 멤브레인 및 에어 브리지 구조는 CMOS 공정 후에 사용 가능하며, 초고주파 회로 설계시 편리성과 유용성을 제시하고 있다.