• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.8
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• pp.808-820
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• 2014

In this paper, we fabricated two on-wafer type DUT(Device-Under-Test)s; a 10-dB attenuator and an amplifier using commercially available MMIC and we proposed the measurement method of the noise parameters for the two fabricated DUTs. Since the 10-dB attenuator DUT is a passive device, its noise parameters can be accurately determined when its S-parameters are measured. In the case of the amplifier DUT, its noise parameters are available in the datasheet. Hence, the measured noise parameters using the proposed method can be assessed by comparing with the known noise parameters. The noise parameter measurement method having been presented by the authors requires the S-parameters of the 8-port network used in the measurement and limited to coaxial type DUTs. When on-wafer probes are included in the 8-port network, the 8-port S-parameters requires the measurements with different kinds of connectors. In this paper, we obtained the 8-port S-parameters using the Smart-Cal function in the network analyzer. The measured noise parameters shows about ${\pm}0.2dB$ fluctuations for $NF_{min}$. Other noise parameters with the frequency change show good agreement with the expected results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.171-176
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• 2021

Die-to-wafer (D2W) hybrid bonding in the multilayer semiconductor manufacturing process is one of wafer direct bonding, and various studies are being conducted around the world. A noteworthy point in the current die-to-wafer process is that a lot of voids occur on the bonding surface of the die during bonding. In this study, as a suggested method for removing voids generated during the D2W hybrid bonding process, a flexible mechanism for implementing convex for die bonding to be applied to the bond head is proposed. In addition, modeling of flexible mechanisms, analysis/design/control/evaluation of static/dynamics properties are performed. The proposed system was controlled by capacitive sensor (lion precision, CPL 290), piezo actuator (P-888,91), and dSpace. This flexure mechanism implemented a working range of 200 ㎛, resolution(3σ) of 7.276nm, Inposition(3σ) of 3.503nm, settling time(2%) of 500.133ms by applying a reverse bridge type mechanism and leaf spring guide, and at the same time realized a maximum step difference of 6 ㎛ between die edge and center. The results of this study are applied to the D2W hybrid bonding process and are expected to bring about an effect of increasing semiconductor yield through void removal. In addition, it is expected that it can be utilized as a system that meets the convex variable amount required for each device by adjusting the elongation amount of the piezo actuator coupled to the flexible mechanism in a precise unit.

• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.175-176
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• 2004

An integrated waveguide optical isolator by wafer direct bonding has been studied. The isolation ratio was found to be 2.9dB in our device. We found that wafer direct bonding between the InP and GGG is effective for the integration of a waveguide optical isolator.

• Journal of the Semiconductor & Display Technology
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• v.4 no.1 s.10
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• pp.49-53
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• 2005

The nanoparticle deposition chamber, which is used for quantum dot semiconductor memory applications, is designed by means of numerical simulation. In this research, the numerical simulations for deposition chamber were performed by commercial software, FLUENT. The deposition of nanoparticles is calculated by diffusion force, thermophoresis and electrophoresis of particles. As a results, when the diffusion force was considered, the most of particles deposited in the wall of deposition chamber. But as considering thermophoresis and electrophoresis of particles, the particles were deposited wafer surface, perfectly.

• Journal of the Semiconductor & Display Technology
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• v.2 no.3
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• pp.1-6
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• 2003

In the rapid changes of the semiconductor manufacturing technologies for early 21st century, it may be safely said that a kernel of terms is the size increase of Si wafer and the size decrease of semiconductor devices. As the size of Si wafers increases and semiconductor device is miniaturized, the units of cleaning processes increase. A present cleaning technology is based upon RCA cleaning which consumes vast chemicals and ultra pure water (UPW) and is the high temperature process. Therefore, this technology gives rise to environmental issue. To resolve this matter, candidates of advanced cleaning processes have been studied. One of them is to apply the electrolyzed water. In this work, electrolyzed water cleaning was compared with various chemical cleaning, using Si wafer surfaces by changing cleaning temperature and cleaning time, and especially, concentrating upon the contact angle. It was observed that contact angle on surface treated with Electrolyzed water cleaning was $4.4^{\circ}$ without RCA cleaning. Amine series additive of high pKa (negative logarithm of the acidity constant) was used to observe the property changes of cathode water.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1296-1301
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• 2003

The chemical mechanical polishing(CMP) is necessarily applied to manufacturing the dielectric layer and metal line in the semiconductor device. The conditioning of polishing pad in CMP process additionally operates for maintaining the removal rate, within wafer non-uniformity, and wafer to wafer non-uniformity. But the fixed abrasive pad(FAP) using the hydrophilic polymer with abrasive that has the swelling characteristic by water owns the self-conditioning advantage as compared with the general CMP. FAP also takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing due to the reduction of abrasive concentration. This paper introduces the manufacturing technique of FAP. And the tungsten CMP using FAP achieved the good conclusion in point of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.9
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• pp.68-79
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• 1997

A six DOF fine manipulator based on magnetic levitation is developed. Since most of magnetic levitation system are inherently unstable, a proposed magnetically levitated fine manipulator is implemented by use of an antagonistic structure to increase stability. From mathematical modeling and experiment, the equations of motion are derived. In addition, a six DOF sensing system is implemented by use of three 2-axis PSD sensors. A model reference-$H_{\infty}$ controller is applied to the system for the position control, In application of the fine manipulator, a wafer probing system is proposed to identify nonfunctional circuts. The probing system requires compliance to avoid destruction of DUT(device under test). A feedfor- ward-PD controllers are presented by the terms of the position accuracy, the settling time and the force accuracy.y.