• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1069-1077
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• 2011

In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.409-409
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• 2014

Recently hexagonal boron nitride (h-BN), III-V compound of boron and nitrogen with strong covalent $sp^2$ bond, is a 2 dimensional insulating material with a large direct band gap up to 6 eV. Its outstanding properties such as strong mechanical strength, high thermal conductivity, and chemical stability have been reported to be similar or superior to graphene. Because of these excellent properties, h-BN can potentially be used for variety of applications such as dielectric layer, deep UV optoelectronic device, and protective transparent substrate. Ultra flat and charge impurity-free surface of h-BN is also an ideal substrate to maintain electrical properties of 2 dimensional materials such as graphene. To synthesize a single or a few layered h-BN, chemical vapor deposition method (CVD) has been widely used by using an ammonia borane as a precursor. Ammonia borane decomposes into hydrogen (gas), monomeric aminoborane (solid), and borazine (gas) that is used for growing h-BN layer. However, very active monomeric aminoborane forms polymeric aminoborane nanoparticles that are white non-crystalline BN nanoparticles of 50~100 nm in diameter. The presence of these BN nanoparticles following the synthesis has been hampering the implementation of h-BN to various applications. Therefore, it is quite important to grow a clean and high quality h-BN layer free of BN particles without having to introduce complicated process steps. We have demonstrated a synthesis of a high quality h-BN monolayer free of BN nanoparticles in wafer-scale size of $7{\times}7cm^2$ by using CVD method incorporating a simple filter system. The measured results have shown that the filter can effectively remove BN nanoparticles by restricting them from reaching to Cu substrate. Layer thickness of about 0.48 nm measured by AFM, a Raman shift of $1,371{\sim}1,372cm^{-1}$ measured by micro Raman spectroscopy along with optical band gap of 6.06 eV estimated from UV-Vis Spectrophotometer confirm the formation of monolayer h-BN. Quantitative XPS analysis for the ratio of boron and nitrogen and CS-corrected HRTEM image of atomic resolution hexagonal lattices indicate a high quality stoichiometric h-BN. The method presented here provides a promising technique for the synthesis of high quality monolayer h-BN free of BN nanoparticles.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.173-181
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• 1992

Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.156-157
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• 2012

단일 셀에서 비휘발성 및 고속의 휘발성 메모리를 모두 구동할 수 있는 다기능 메모리는 모바일 기기 및 embedded 장치의 폭발적인 성장에 있어 그 중요성이 커지고 있다. 따라서 최근 이러한 fusion기술을 응용한 unified RAM (URAM)과 같은 다기능 메모리의 연구가 주목 받고 있다. 이러한 다목적 메모리는 주로 silicon on insulator (SOI)기반의 1T-DRAM과 SONOS기술 기반의 비휘발성 메모리의 조합으로 이루어진다. 하지만 이런 다기능 메모리는 주로 단결정기반의 SOI wafer 위에서 구현되기 때문에 값이 비싸고 사용범위도 제한되어 있다. 따라서 이러한 다기능메모리를 다결정 실리콘을 이용하여 제작한다면 기판에 자유롭게 메모리 적용이 가능하고 추후 3차원 적층형 소자의 구현도 가능하기 때문에 다결정실리콘 기반의 메모리 구현은 필수적이라고 할 수 있겠다. 본 연구에서는 다결정실리콘을 이용한 channel recessed구조의 다기능메모리를 제작하였으며 각 1T-DRAM 및 NVM동작에 따른 memory 특성을 살펴보았다. 실험에 사용된 기판은 상부 비정질실리콘 100 nm, 매몰산화층 200 nm의 SOI구조의 기판을 이용하였으며 고상결정화 방법을 이용하여 $600^{\circ}C$ 24시간 열처리를 통해 결정화 시켰다. N+ poly Si을 이용하여 source/drain을 제작하였으며 RIE시스템을 이용하여 recessed channel을 형성하였다. 상부 ONO게이트 절연막은 rf sputter를 이용하여 각각 5/10/5 nm 증착하였다. $950^{\circ}C$ N2/O2 분위기에서 30초간 급속열처리를 진행하여 source/drain을 활성화 하였다. 계면상태 개선을 위해 $450^{\circ}C$ 2% H2/N2 분위기에서 30분간 열처리를 진행하였다. 제작된 Poly Si MFM에서 2.3V, 350mV/dec의 문턱전압과 subthreshold swing을 확인할 수 있었다. Nonvolatile memory mode는 FN tunneling, high-speed 1T-DRAM mode에서는 impact ionization을 이용하여 쓰기/소거 작업을 실시하였다. NVM 모드의 경우 약 2V의 memory window를 확보할 수 있었으며 $85^{\circ}C$에서의 retention 측정시에도 10년 후 약 0.9V의 memory window를 확보할 수 있었다. 1T-DRAM 모드의 경우에는 약 $30{\mu}s$의 retention과 $5{\mu}A$의 sensing margin을 확보할 수 있었다. 차후 engineered tunnel barrier기술이나 엑시머레이저를 이용한 결정화 방법을 적용한다면 device의 특성향상을 기대할 수 있을 것이다. 본 논문에서는 다결정실리콘을 이용한 다기능메모리를 제작 및 메모리 특성을 평가하였다. 제작된 소자의 단일 셀 내에서 NVM동작과 1T-DRAM동작이 모두 가능한 것을 확인할 수 있었다. 다결정실리콘의 특성상 단결정 SOI기반의 다기능 메모리에 비해 낮은 특성을 보여주었으나 이는 결정화방법, high-k절연막 적용 및 engineered tunnel barrier를 적용함으로써 해결 가능하다고 생각된다. 또한 sputter를 이용하여 저온증착된 O/N/O layer에서의 P/E특성을 확인함으로써 glass위에서의 MFM구현의 가능성도 확인할 수 있었으며, 차후 system on panel (SOP)적용도 가능할 것이라고 생각된다.

• Bulletin of the Korean Chemical Society
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• v.32 no.1
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• pp.263-272
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• 2011

Highly luminescent and monodisperse InP quantum dots (QDs) were prepared by a non-organometallic approach in a non-coordinating solvent. Fatty acids with well-defined chain lengths as the ligand, a non coordinating solvent, and a thorough degassing process are all important factors for the formation of high quality InP QDs. By varying the molar concentration of indium to ligand, QDs of different size were prepared and their absorption and emission behaviors studied. By spin-coating a colloidal solution of InP QD onto a silicon wafer, InP QD thin films were obtained. The thickness of the thin films cured at 60 and $200^{\circ}C$ were nearly identical (approximately 860 nm), whereas at $300^{\circ}C$, the thickness of the thin film was found to be 760 nm. Different contrast regions (A, B, C) were observed in the TEM images, which were found to be unreacted precursors, InP QDs, and indium-rich phases, respectively, through EDX analysis. The optical properties of the thin films were measured at three different curing temperatures (60, 200, $300^{\circ}C$), which showed a blue shift with an increase in temperature. It was proposed that this blue shift may be due to a decrease in the core diameter of the InP QD by oxidation, as confirmed by the XPS studies. Oxidation also passivates the QD surface by reducing the amount of P dangling bonds, thereby increasing luminescence intensity. The dielectric properties of the thin films were also investigated by capacitance-voltage (C-V) measurements in a metal-insulator-semiconductor (MIS) device. At 60 and $300^{\circ}C$, negative flat band shifts (${\Delta}V_{fb}$) were observed, which were explained by the presence of P dangling bonds on the InP QD surface. At $300^{\circ}C$, clockwise hysteresis was observed due to trapping and detrapping of positive charges on the thin film, which was explained by proposing the existence of deep energy levels due to the indium-rich phases.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.173-173
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• 2010

Recently, a patterned sapphire substrate (PSS) has been intensively used as one of the effective ways to reduce the dislocation density for the III-nitride epitaxial layers aiming for the application of high-performance, especially high-brightness, light-emitting diodes (LEDs). In this paper, we analyze the growth kinetics of the atoms and crystalline quality for the undopped-GaN depending on the facets of the pattern fabricated on a sapphire substrate. The effects of the PSS on the device characteristics of InGaN/GaN LEDs were also investigated. Several GaN samples were grown on the PSS under the different growth conditions. And the undoped-GaN layer was grown on a planar sapphire substrate as a reference. For the (002) plane of the undoped-GaN layer, as an example, the line-width broadening of the x-ray diffraction (XRD) spectrum on a planar sapphire substrate is 216.0 arcsec which is significantly narrower than that of 277.2 arcsec for the PSS. However, the line-width broadening for the (102) plane on the planar sapphire substrate (363.6 arcsec) is larger than that for the PSS (309.6 arcsec). Even though the growth parameters such as growth temperature, growth time, and pressure were systematically changed, this kind of trend in the line-width broadening of XRD spectrum was similar. The emission wavelength of the undoped-GaN layer on the PSS was red-shifted by 5.7 nm from that of the conventional LEDs (364.1 nm) under the same growth conditions. In addition, the intensity for the GaN layer on the PSS was three times larger than that of the planar case. The spatial variation in the emission wavelength of the undoped-GaN layer on the PSS was statistically ${\pm}0.5\;nm$ obtained from the photoluminescence mapping results throughout the whole wafer. These results will be discussed in terms of the mixed dislocation depending on the facets and the period of the patterns.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.1
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• pp.18-26
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• 2016

The semiconductor industry is one of the key industries of Korea, which has continued growing at a steady annual growth rate. Important technology for the semiconductor industry is high integration of devices. This is to increase the memory capacity for unit area, of which key is photolithography. The photolithography refers to a technique for printing the shadow of light lit on the mask surface on to wafer, which is the most important process in a semiconductor manufacturing process. In this study, the width and step-height of wafers patterned through this process were measured to ensure uniformity. The widths and inter-plate heights of the specimens patterned using photolithography were measured using transmissive digital holography. A transmissive digital holographic interferometer was configured, and nine arbitrary points were set on the specimens as measured points. The measurement of each point was compared with the measurements performed using a commercial device called scanning electron microscope (SEM) and Alpha Step. Transmission digital holography requires a short measurement time, which is an advantage compared to other techniques. Furthermore, it uses magnification lenses, allowing the flexibility of changing between high and low magnifications. The test results confirmed that transmissive digital holography is a useful technique for measuring patterns printed using photolithography.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.