• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.523-524
• /
• 2007

This paper discusses the planarization process of thick copper film structure used for power supply device. Chemical mechanical polishing(CMP) has been used to remove a metal film and obtain a surface planarization which is essential for the semiconductor devices. For the thick metal removal, however, the long process time and other problems such as dishing, delamination and metal layer peeling are being issued, Compared to the traditional CMP process, Electro-chemical mechanical planarization(ECMP) is suggested to solve these problems. The two-step process composed of the ECMP and the conventional CMP is used for this experiment. The first step is the removal of several tens ${\mu}m$ of bulk copper on patterned wafer with ECMP process. The second step is the removal of residual copper layer aimed at a surface planarization. For more objective comparison, the traditional CMP was also performed. As an experimental result, total process time and process defects are extremely reduced by the two-step process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.169-170
• /
• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.2
• /
• pp.101-106
• /
• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2005.09a
• /
• pp.35-40
• /
• 2005

The demand for small and high-capacity optical data storage devices has rapidly increased. The areal density of optical disk is increased using higher numerical aperture objective lens and shorter wavelength source. A wafer-scale stacked micro objective lens with a numerical aperture of 0.85 and a focal length of 0.467mm for the 405nm blue- violet laser was designed and fabricated. A diffractive optical element (DOE) was used to compensate the spherical aberration of the objective lens. Among the various fabrication methods for micro DOE, the UV-replication process is more suitable for mass-production. In this study, an 8-stepped DOE pattern as a master was fabricated by photolithography and reactive ion etching process. A flexible mold was fabricated for improving the releasing properties and shape accuracy in UV-molding process. In the replication process, the effects of exposing time and applied pressure on the replication quality were analyzed. Finally, the shapes of master, mold and molded pattern were measured by optical scanning profiler. The deviation between the master and the molded DOE was less than 0.1um. The efficiency of the molded DOE was measured by DOE efficiency measurement system which consists of laser source, sample holder, aperture and optical power meter, and the measured value was $84.5\%$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.2
• /
• pp.158-163
• /
• 2023

Recently, the global demands for high voltage power semiconductors are increasing across various industrial fields. The use of electric cars with high safety and convenience is becoming practical, and IGBT modules of 3.3 kV and 1.2 kA or higher are used for electric locomotives. Delicate design and advanced process technology are required, and research on the optimization of high-voltage IGBT parts is urgently needed in the industry. In this study, we attempted to design a simulation process through TCAD (technology computer-aid design) software to optimize the process conditions of the fielding process among the core unit processes for an especial high yield voltage. As well, the prior circuit technology design and a ring pattern with a large number of ring formation structures outside the wafer similar to the chip structure of other companies were constructed for 3.3 kV NPT-IGBT through a unit process demonstration experiment. The ring pattern was designed with 21 rings and the width of the ring was 6.6 ㎛. By changing the spacing between patterns from 17.4 ㎛ to 35.4 ㎛, it was possible to optimize the spacing from 19.2 ㎛ to 18.4 ㎛.

• Journal of Convergence Korean Medicine
• /
• v.2 no.1
• /
• pp.5-12
• /
• 2021

Objectives: The purpose of this study is to fabricate an ultra-fine ginsenoside particle atomizer that can provide a new treatment method by delivering ginsenoside components that have a therapeutic effect on respiratory diseases directly to the lungs. Methods: We fabricated the AAO vibrating mesh by using the micromachining process. The starting substrate of an AAO wafer has a 350nm pore diameter with 50㎛ thickness. A photomask having several 5㎛ opening holes with a 100㎛ pitch was used to separate each nanopore nozzle. The photoresist structure was optimized to pattern the nozzle area during the lift-off process precisely. The commercial vibrating mesh was removed from OMRON's NE-U100 product, and the fabricated AAO vibrating mesh was installed. A diluted sample of 20mL with 30% red ginseng concentrate was prepared to atomize from the device. Results: As a result of liquid chromatography analysis before spraying the ginsenoside solution, ginsenoside components such as 20S-Rg3, 20R-Rg3, and Rg5 were detected. After spraying through the AAO vibrating mesh, ginsenosides of the same component could be detected. Conclusion: A nutrient solution containing ginsenosides was successfully sprayed through the AAO vibrating mesh with 350 nm selective pores. In particular, during the atomizing experiment of ginsenoside drug solution having excellent efficacy in respiratory diseases, it was confirmed that atomizing through the AAO vibrating mesh while maintaining most of the active ingredients was carried out.

• Applied Chemistry for Engineering
• /
• v.35 no.3
• /
• pp.260-265
• /
• 2024

To synthesize an antistatic material for use in semiconductor wafer transport trays, in-situ polymerization of poly(methyl methacrylate) (PMMA) and polyurethane (PU) incorporating carbon nanotubes was designed and conducted. The newly synthesized composites were evaluated for their thermal and electrical conductivity properties under conditions mimicking commercial device manufacturing processes. Comparative analysis of their respective performances revealed that both PMMA and PU containing carbon nanotubes exhibited enhanced thermal properties and superior electrical conductivity as the nanotube content increased. Morphology of the composites synthesized via in-situ polymerization was confirmed to be excellent through FE-SEM analysis, demonstrating good dispersibility. Both PMMA and PU incorporating carbon nanotubes showed outstanding surface resistance values of 10³ Ω/□, indicating their suitability as antistatic materials for semiconductor applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.137-137
• /
• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Journal of Sensor Science and Technology
• /
• v.23 no.3
• /
• pp.185-191
• /
• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.