• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.24 no.2
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• pp.155-159
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• 2015

Light emitting devices (LEDs) are widely used in the liquid crystal display (LCD) industry, especially for LCD back light units. Therefore, much research has been performed to minimize manufacturing costs. However, the current process does not process LED chips from broken substrates even though the substrate is expensive sapphire wafer. This is because the broken substrates lose their alignment marks. After pre-processing, LED dies are glued onto blue tape to continue post-processing. If auxiliary alignment marks are stamped on the blue tape, post-processing can be performed using some of the LED dies from broken substrates. In this paper, a novel stamper module that can stamp the alignment mark on the blue tape is proposed, designed, and fabricated. In testing, the stamper was reliable even after a few hundred stamps. The module can position the stamp and apply the pattern effectively. By using this module, the LED industry can reduce manufacturing costs.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.481-482
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• 2006

Chemical-mechanical polishing, the dominant technology for LSI planarization, is trending to play an important function in micro-electro mechanical systems (MEMS). However, MEMS CMP process has a couple of different characteristics in comparison to LSI device CMP since the feature size of MEMS is bigger than that of LSI devices. Preliminary CMP tests are performed to understand material removal rate (MRR) with blanket wafer under a couple of polishing pressure and velocity. Based on the blanket CMP data, this paper focuses on the consumable approach to enhance MEMS CMP by the adjustment of slurry and pad. As a mechanical tool, newly developed microstructured (MS) pad is applied to compare with conventional pad (IC 1400-k Nitta-Haas), which is fabricated by micro melding method of polyurethane. To understand the CMP characteristics in real time, in-situ friction force monitoring system was used. Finally, the topography change of poly-si MEMS structures is compared according to the pattern density, size and shape as polishing time goes on.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.206-210
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• 2005

The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/$cm^{2}$-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.154-159
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• 2005

The next generation of optical storage systems requires higher numerical aperture (NA) objective lenses and shorter wavelength laser in order to improve the unit areal density. A blu-ray technology satisfies a miniaturization and a high capacity which are the requirements of the portable device. In this paper, we analyze the optical performance of hybrid micro lens and do active alignment. The hybrid micro lens is manufactured by using a wafer based fabrication technology. Optical components of hybrid micro lens are evaluated. The measurement of the optical power, the spot size and the wavefront error awe performed to evaluate the hybrid micro lens with NA 0.85. Using the measured data, we estimate if the performance of hybrid micro lens corresponds to the designed performance. After the performance of hybrid micro lens is evaluated, the integrated optical pickup and the hybrid micro lens are assembled by active alignment using UV curing and the optical performance of SFFOP is satisfied with BD specifications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.22-27
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• 2013

Detailed study on how the plasma process during the sidewall spacer formation suppresses the formation of silicide is done. In non-patterned wafer test, it is found that both fluorocarbon reactive ion etch (RIE) and TEOS plasma-enhanced deposition processes modify the Si surface so that the silicide reaction is chemically inhibited or suppressed. In order to investigate the cause of the chemical modification, we analyze the elements on the silicon surface through Auger Electron Spectroscopy (AES). From the AES result, it is found that the carbon induces chemical modification which blocks the reaction between silicon and nickel. Thus, protecting the surface from the carbon-containing plasma process prior to nickel deposition appears critical in successful silicide formation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.121-122
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• 2008

Lithium Niobate (LN:LiNbO3) is a compound of niobium, lithium and oxygen. The characteristics of LN are piezoelectricity, ferroelectricity and photoelectricity, and which is widely used in surface acoustic wave (SAW). To manufacture LN device, the LN surface should be a smooth surface and defect-free because of optical property, but the LN material is processed difficult by traditional processes such as grinding and mechanical polishing (MP) because of its brittleness. To decrease defects, chemical mechanical polishing (CMP) was applied to the LN wafer. In this study, the suitable parameters scuh as pressure and relative velocity, were investigated for the LN CMP process. To improve roughness, the LN CMP was performed using the parameters that were the highest removal rate among process parameters. And, evaluation of optical property was performed by the optical reflectance and non-linear characteristic.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.9
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• pp.707-713
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was requirdfo the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gest thinner, micro-scratches are becoming as major defects. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}{\textrm}{m}$ point of use (POU) filter, which is depth-type filter and has 80% filtering efficiency for the 1.0${\mu}{\textrm}{m}$ size particle. In this paper, we studied the relationship between defect generation and polished wafer counts to understand the exact efficiency fo the slurry filteration, and to find out the appropriate pad usage. Our experimental results showed that it sis impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate, and to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of depth type filter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.