• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.62-69
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• 2007

Micromanipulator is a device that manipulates an object with high precision. Generally, a parallel-type robot has inherently higher precision than a serial-type robot. In most cases, the use of flexure hinge mechanisms is the most appropriate approach to micromanipulators. The micromanipulator is basically required that have high natural frequency and sufficient workspace. However, previous designs are hard to satisfy the required workspace and natural frequency, simultaneously, because the previous micromanipulators are coupled designs. Therefore, this paper suggests a new design parameter as displacement amplifier and new design procedure based on semi-coupled design in axiomatic design. As a consequence the spatial 3-DOF micromanipulator which is chosen as an exemplary device has natural frequency of 500Hz and workspace of $-0.5^{\circ}{\sim}0.5^{\circ}$. To investigate the effectiveness of the displacement amplifier, simulation and experiment are performed.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.6
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• pp.507-514
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• 2022

This study proposes an optimal design process for a high-frequency transformer that has a large leakage inductance for dual-active-bridge converters. Notably, conventional design processes have large errors in designing leakage transformers because mathematically modeling the leakage inductance of such transformers is difficult. In this work, the geometric parameters of a shell-type transformer are identified, and finite element analysis(FEA) simulation is performed to determine the magnetization inductance, leakage inductance, and copper loss of various shapes of shell-type transformers. Regression models for magnetization and leakage inductances and copper loss are established using the simulation results and the machine learning technique. In addition, to improve the regression models' performance, the regression models are tuned by adding featured parameters that consider the physical characteristics of the transformer. With the regression models, optimal high-frequency transformer designs and the Pareto front (in terms of volume and loss) are determined using NSGA-II. In the Pareto front, a desirable optimal design is selected and verified by FEA simulation and experimentation. The simulated and measured leakage inductances of the selected design match well, and this result shows the validity of the proposed design process.

• Journal of Communications and Networks
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• v.5 no.2
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• pp.141-149
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• 2003

In this paper, we investigate design criteria and the performance of the space-frequency bit-interleaved coded modulation (SF-BICM) systems in frequency-selective Rayleigh fading channels. To determine the key parameters that affect the performance of SF-BICM, we derive the pairwise error probability (PEP) in terms of the determinant of the matrix corresponding to any two codewords. We prove that the bit-interleavers do the function of distributing the nonzero bits uniformly such that two or more nonzero bits are seldom distributed into the symbols that are transmitted in the same frequency bin. This implies that the bit-interleavers transform an SF-BICM system into an equivalent 1-antenna system. Based on this, we present design criteria of SFBICM systems that maximizes the diversity order and the coding gain. Then, we analyze the performance of SF-BICM for the case of 2-transmit antennas and 2-multipaths by deriving a frame error rate (FER) bound. The derived bound is accurate and requires only the distance spectrum of the constituent codes of SF-BICM. Numerical results reveal that the bound is tight enough to estimate the performance of SF-BICM very accurately.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.51-58
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• 2015

In order to decrease the size of a switch mode power supply, high switching frequency can be an efficient way to reduce the size of passive components in the converter. In this paper, a 500-kHz high-frequency LLC resonant converter is proposed with an accurate design method of magnetizing inductance, as well as the relationship between the switching frequency and the size of the passive components. Simulation and experimental results are presented to verify the proposed methods and equations, including the temperature data of each passive and active device of the converter. Using those results, dominant power losses in the prototype converter under 500-kHz high-frequency operation are investigated, compared with the results from a 100-kHz converter. In addition, operating waveforms and power conversion efficiency will be shown to obtain design considerations for the high switching frequency LLC resonant converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.1
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• pp.77-84
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• 2012

This paper describes the process of optimal resonant frequency design with full-bridge series-loaded resonant dc-dc converter in a high efficiency 3.3 kW on-board battery charger application for Electric Vehicles and Plug-in Hybrid Electric Vehicles. The optimal range of resonant frequency and switching frequency used for ZVS are determined by considering trade-off between loss of switching devices and resonant network with size of passive/magnetic devices. In addition, it is defined charging region of battery, the load of on-board charger, as the area of load by deliberating the characteristic of resonant. It is verified the designed frequency band by reflecting the defined area on resonant frequency.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.26 no.5B
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• pp.489-499
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• 2006

The Potential Flood Damage (PFD) is widely used for representing the degree of potential of flood damage. However, this cannot be related with the design frequency of river basin and so we have difficulty in the use of water resources field. Therefore, in this study, the concept of Potential Risk for Flood Damage Occurrence (PRFD) was introduced and estimated, which can be related to the design frequency. The PRFD has three important elements of hazard, exposure, and vulnerability. The hazard means a probability of occurrence of flood event, the exposure represents the degree that the property is exposed in the flood hazard, and the vulnerability represents the degree of weakness of the measures for flood prevention. Those elements were devided into some sub-elements. The hazard is explained by the frequency based rainfall, the exposure has two sub-elements which are population density and official land price, and the vulnerability has two sub-elements which are undevelopedness index and ability of flood defence. Each sub-elements are estimated and the estimated values are rearranged in the range of 0 to 100. The Analytic Hierarchy Process (AHP) is also applied to determine weighting coefficients in the equation of PRFD. The PRFD for the Anyang river basin and the design frequency are estimated by using the maximum rainfall. The existing design frequency for Anyang river basin is in the range of 50 to 200. And the design frequency estimation result of PRFD of this study is in the range of 110 to 130. Therefore, the developed method for the estimation of PRFD and the design frequency for the administrative districts are used and the method for the watershed and the river channel are to be applied in the future study.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.208-211
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• 2000

This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.175-182
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• 2007

In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.

• Journal of information and communication convergence engineering
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• v.7 no.3
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• pp.399-403
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• 2009

In IEEE 802.15.1 (Bluetooth) Ad-hoc networks, the frequency is resolved by the specific part of the digits of the Device clock and the Bluetooth address of the Master device in a given piconet. The piconet performs a fast frequency hopping scheme over 79 carriers of 1-MHz bandwidth. Since there is no coordination between different piconets, packet collisions may occur if two piconets are located near one another. In this paper, we proposed a software/hardware co-design of an adaptive frequency decision mechanism so that more than two different kinds of wireless devices can stay connected without frequency collision. Suggested method was implemented with C program and HDL (Hardware Description Language) and automatically synthesized and laid out. The adaptive frequency hopping circuit was implemented in a prototype and showed its operation at 24MHz correctly.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.