• International conference on construction engineering and project management
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• 2015.10a
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• pp.28-29
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• 2015

The tire production facility is a large-scale construction with the complexity of a manufacturing process. The process utilities should be wide-ranging as an effective arrangement of them is highly important. All the necessary information should be clarified together with the manufacturer at the basic planning stage, and this design should be developed to comply with the local culture and regulations. It is important to carry out more advanced engineering in terms of process, cost and quality, even if it is difficult to standardize due to the cultural and geographical conditions and regulations. The key point is to reflect all the given conditions and make a clear design during the design stage, to eliminate the problems after the construction has begun. Another key point is the delivery system, which must be totally managed from the initial design stage until the construction stage by proven companies. Flexibility, quick action, and single responsibility will be the fundamental features in all the steps of the project.

• International Journal of High-Rise Buildings
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• v.1 no.3
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• pp.203-209
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• 2012

The purpose of this paper is to present the state of practice being used in the Philippines for the performance-based seismic design of reinforced concrete tall buildings. Initially, the overall methodology follows "An Alternative Procedure for Seismic Analysis and Design of Tall Buildings Located in the Los Angeles Region, 2008", which was developed by Los Angeles Tall Buildings Structural Design Council. After 2010, the design procedure follows "Tall Buildings Initiative, Guidelines for Performance-Based Seismic Design of Tall Buildings, 2010" developed by Pacific Earthquake Engineering Research Center (PEER). After the completion of preliminary design in accordance with code-based design procedures, the performance of the building is checked for serviceable behaviour for frequent earthquakes (50% probability of exceedance in 30 years, i.e,, with 43-year return period) and very low probability of collapse under extremely rare earthquakes (2% of probability of exceedance in 50 years, i.e., 2475-year return period). In the analysis, finite element models with various complexity and refinements are used in different types of analyses using, linear-static, multi-mode pushover, and nonlinear-dynamic analyses, as appropriate. Site-specific seismic input ground motions are used to check the level of performance under the potential hazard, which is likely to be experienced. Sample project conducted using performance-based seismic design procedures is also briefly presented.

• Korean Journal of Computational Design and Engineering
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• v.4 no.4
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• pp.318-326
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• 1999

Recently, electronic systems including computers have been rapidly shrinking in size while at the same time the complexity and the capability of these systems continue to grow/sup [1]/. Thus, system volumes have decreased as system power has increased, resulting in dramatic increases in system heat density. The high temperature of the computer system is considered as the major reason for low performance and shortening life of the product. It is necessary to solve this problem due to the heat density increased and to develop the design skill of the computer cabinet according to miniaturization. M4500 desk-top computer was selected for analyzing the thermal management inside cabinet. The cabinet volume, the configuration of the heating devices, the size and location of air ventilation, and the fan selection have been investigated as the important parameters to find out an optimal cabinet design. The objectives of this project were to analyze which design parameters would affect cooling performance by thermal strategy, to design an optimal model, and to measure the temperatures of the main parts to confirm the effect of the thermal design. The temperatures of each part of the optimal model were compared with those of the existing model. As a result. the volume of this miniaturized model was about 16% smaller than that of M4500 without any change in operating performance.

• Journal of the Korea Furniture Society
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• v.17 no.3
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• pp.69-78
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• 2006

Recently, the aspect of consumers' preference for design has been changed to a pattern of respect for personality, based on 'personal value of passion'. The differentiated personal passion of modern people does not allow them to select mass-produced industrial product, and leads them to choose life style different from others. Specially, consumers want to express. their differentiated personality by preferring and possessing the originally designed products. Therefore, the originally designed products that are clearly identifiable become the object of consumers' consideration, and stimulate the consumers' desire to purchase. According to new needs of consumers, it is required to reconsider the old design pattern of furniture based on simplicity and propose new design for furniture to meet the needs of consumers. Mass production has resulted in a strong focus on simplicity rather than difficulty and complexity of the production process. This tendency shows the design pattern that leans toward one side excluding the expression of correlative concept among design elements. This one sided design leads modern people to have no personality, and shows only simple and uniform expression of passion. Therefore, this paper is purposed to develop furniture with more personality by applying correlative concept that has been taken less seriously in the field of design to furniture design.

• Journal of the Architectural Institute of Korea Structure & Construction
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• v.35 no.2
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• pp.29-36
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• 2019

Modular construction has benefits such as short construction duration and high productivity owing to the production in factory and owing to simultaneous on-site work. However, rework occurs in modular construction and the rework affects the efficiency of modular construction. The almost of causes of rework are exist in design process. To reduce the cause of rework, the information flow of the design process should be managed and the plan to reduce rework should be included. However, the modular construction has complex process because of impeded unit production so it is hard to manage the information flow in design process. Moreover, when the plan to reduce rework is included, the design process will be more complicated. Therefore, the objective of this research is to suggest the design process including the rework reduction plan and to alleviate the complexity of design process by using Dependency Structure Matrix(DSM). By using DSM, the iteration and feedback in design process is reduced and it can be expected that rework in modular project can be reduced by using suggested design process.

• International Journal of Control, Automation, and Systems
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• v.1 no.3
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• pp.339-350
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• 2003

In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.5
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• pp.827-834
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• 2020

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the microwave airborne radar. Unlike the basic mixer design method, the gate bias voltage, at which the third-harmonic component of the Local frequency (LO) is the maximum, is selected using a frequency multiplier theory to maximize the third-harmonic mixing component at the intermediate frequency (IF). The proposed harmonic mixer was designed and manufactured using a commercial GaAs MESFET device in a plastic package, and it was possible to improve the high conversion loss, circuit complexity, high cost, and manufacturing complexity of the existing microwave mixer. The harmonic mixer using the proposed design method has a -8 ~ -10 dB conversion loss by pumping 11.5 GHz LO with a +5 dBm level when operating from 33.0 GHz to 36.0 GHz and the 1-dB gain compression point (P1dB) of 0 dBm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.