• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• ETRI Journal
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• v.18 no.4
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• pp.215-227
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• 1997

We propose a new method to eliminate completely the redundant elements in a CDMA (code division multiple access) mobile system. First, we define multilevel logic operation (MLO), which is a new concept to deal with the multilevel logic signals. We prove that the conventional binary logic concept is a subset of the MLO concept. The multilevel logic signal can be directly controlled by using this MLO in place of the binary operation. We applied the MLO to the CDMA base station modulator (BSM) in order to reduce the hardware complexity. In the case of a 3-sectorized cell, this method helps reduce the complexity down the level of below 1% of the conventional CDMA BSM for spreading and filtering, and to 50% for Walsh covering.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.69-72
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• 1999

In this paper, an efficient time domain equalization algorithm for discrete wavelet multitone(DWMT) data transmission is developed. In this algorithm, the time domain equalizer(TEQ) consists of two stages, i.e., the channel impulse response shortening equalizer(TEQ-S) in the first stage and the channel frequency flattening equalizer(TEQ-F) in the second stage. TEQ-S reduces the length of transmission channel impulse response to decrease intersymbol interference(ISI) followed by TEQ-F that enhances the channel frequency response characteristics to the level of an ideal channel, hence diminishes the bit error rate. TEQ-S is implemented using the least-squares(LS) method, while TEQ-F is designed by using the least mean-square(LMS) algorithm. Since DWMT system also requires of the frequency domain equalizer in order to further reduce ICI and ISI the hardware complexity is an another concern. However, by adopting an well designed and trained TEQ, the hardware complexity of the whole DWMT system can be greatly reduced.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.4 no.1
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• pp.11-15
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• 1986

In the new futre, computer system designers are expeted to bring more computer power to more people than is currently feasible. At the same time. it is reasonable for the computer system desigers to expect the computer architects to prodce hardware structures incorporating system algorithms of greated complexity so that more of the general instructions go to serving the users. In the past, the architect has delivered more computing to the user by constructing bigger and faster central processors, possibly connecting two or three CPUs together This approach has its limitations, in cost, complexity and reliability. In this paper, we first briefly discuss the hardware environment on which Hydra was implemented, then discuss the philosophy on which the system is based, and finally exhibit the protection mechanism.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.394-396
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• 2000

Currently, lots of research s going on in the field of the load distribution within HTTP. RR-DNS and SWEB are the most representative load distribution research. But, there are still many problems: unbalancing of load, load increase of web server and cost increase. Also, clients that require lots of data like multimedia happens to increase network load. To solve these, research about client/agent/server architecture is going on. But, the clients must know the agent's address and there are complexity and migration problems for design of such as protocol. This paper proposes TBSMS that is capable of choosing the optimal server considering the service capacity of the server as well as the network load. This paper demonstrates that TBSMS uses the web to solve the problem that client must know the agent's address and uses SNMP to solve the complexity and migration problem.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.30-36
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• 1990

Context-free language can be recognized by Cocke-Younger-Kasami algorithm. This algorithm is a class of polyadic-nonserial dynamic programming technique and has the O(n**3) time complexity. In this paper, a one-dimensional systolic array for recognition of context-free language is designed. The designed triangle type two-dimensional array is projected and transformed to an one-dimensional array. The designed one-dimensional array has n processing elements and \ulcornern+1)/2\ulcorner(n-1)+3n-1 time units to process the algorithm (n is the length of input string). The time complexity is O(n\ulcorner.

• Journal of Aerospace System Engineering
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• v.7 no.2
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• pp.29-34
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• 2013

Safety requirements for aircraft and system functions include minimum performance constraints for both availability and integrity of the function. These safety requirements should be determined by conducting a safety assessment. The depths and contents of aircraft system safety assessment vary depending on factors such as the complexity of the system, how critical the system is to flight safety, what volume of experience is available on the type of system and the novelty and complexity of the technologies being used. Requirements that are defined to prevent failure conditions or to provide safety related functions should be uniquely identified and traceable through the levels of development. This will ensure visibility of the safety requirements at the software and electronic hardware design level. This paper has prepared to study on promoting the efficiency of establishing hierarchical safety requirements from aircraft level function to item level through system safety processes.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.13-24
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• 2003

In this study, we propose a scheduling analysis method of the Flexible management system using the transitive matrix. The Scheduling problem is a combination-optimization problem basically, and a complexity is increased exponentially for a size of the problem. To reduce an increase of a complexity, we define that the basic unit of concurrency (short BUC) is a set of control flows based on behavioral properties in the net. And we propose an algorithm to divide original system into some BUC. To sum up, we divide a petri net model of the Flexible management system Into the basic unit of concurrency through the division algorithm using the transitive matrix. Then we apply it to the division-scheduling algorithm to find an efficient scheduling. Finally, we verify its efficiency with an example.