• Title/Summary/Keyword: Design Verification Process

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Study on a Verification of System Requirements by using Verification Matrix and Requirements Traceability (검증매트릭스(Verification Matrix)를 활용한 요구사항 검증방안 연구)

  • Chung, Kyung-Ryul;Choi, Chun-Ho;Park, Chan-Young;Han, Suk-In
    • Proceedings of the KSR Conference
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    • 2010.06a
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    • pp.1821-1828
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    • 2010
  • In this study we suggest a method of optimization of verification hierarchy structure and system requirements management by using a verification matrix with traceability consideration. Verification items were gathered in the process of CDR(Critical Design Review), and analyzed with respect to requirements traceability structure. Missed or overlapped items were adjusted, and cross-correlated items between sub-systems were clustered and rearranged in order to structurize verification requrements (VRs). Those VRs are to be used as a guideline for the test and evaluation planning, development of test items and procedure, and system requirements management throughout the system integration stages.

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A Study on the Process Design and Deformation Analysis for Pressure Vessels by Finite Element Method (유한요소법을 활용한 압력용기의 설계 및 성형해석에 관한 연구)

  • 한규택
    • Journal of Advanced Marine Engineering and Technology
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    • v.22 no.4
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    • pp.460-467
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    • 1998
  • The investigation deals with the manufacturing process design and deformation analysis for seamless pressure vessels Axisymmetric multistage deep drawing is a complex and important sheet metal forming process in the industry. In this study the process design for large size cylindrical shells with various thickness is performed and a general guideline for forming process design of pressure vessels will be suggested. Thus in this paper for the verification of the forming process design the forming analysis of pressure vessels will be carried out by PAM-STAMP which is on the basis of finite element analysis. In this case the formability of pressure vessels is evaluated using the results of computer simulation.

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Multi-Stage Cold Forging Process Design with A* Searching Algorithm (탐색 알고리즘을 이용한 냉간 단조 공정 설계)

  • 김홍석;임용택
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 1995.10a
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    • pp.30-36
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    • 1995
  • Conventionally design for multi-stage cold forging depends on the designer's experience and decision-making. Due to such non-deterministic nature of the process sequence design, a flexible inference engine is needed for process design expert system. In this study, A* searching algorithm was introduced to arrive at the vetter process sequence design considering the number of forming stages and levels of effective strain, effective stress, and forming load during the porcess. In order to optimize the process sequence in producing the final part, cost function was defined and minimized using the proposed A* searching algorithm. For verification of the designed forming sequences, forming experiments and finite element analyses were carried out in the present investigation. The developed expert system using A* searching algorithm can produce a flexible design system based on changes in the number of forming stages and weights.

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Design and Implementation of Co-Verification Environments based-on SystemVerilog & SystemC (SystemVerilog와 SystemC 기반의 통합검증환경 설계 및 구현)

  • You, Myoung-Keun;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.274-279
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    • 2009
  • The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

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A Study of PLC Simulation for Transport System in Virtual Environment (가상환경 기반의 컨베이어 시스템 검증을 위한 제어 시뮬레이션 연구)

  • Ko, Min-Suk;Park, Sang-Chul
    • Korean Journal of Computational Design and Engineering
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    • v.17 no.4
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    • pp.274-281
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    • 2012
  • This paper proposed a control simulation method for design and verification of the transport system in an automobile assembly line based on digital manufacturing system. The design of the transport system involves two major activities: mechanical design (device specification) and electrical design (device behavior and system control). Conventionally, the simulation and emulation system of the transport system focuses on the abstract level, which mainly deals with design verification, alternative comparison, and system diagnosis. Although it can provide overall system visibility in monitoring how well it works in the process and view, its simulation models are not sufficiently realistic to be used for a detailed design or for implementation purposes. In this paper, a digital simulation model for a transport system in an automotive assembly line is constructed by adapting a digital manufacturing methodology. We use the concept of the "Virtual Probe", which transport a carrier instead of the belt of the conveyor. In conclusion, the proposed method is valuable in the process of test run in the shop floor. This method would reduce the time and effort for validating the manufacturing system and improve the productivity and integrity of the control program.

Design Verification of APR1400 Reactor Vessel Through Re-engineering Approach

  • Mutembei, Mutegi Peter;Namgung, Ihn
    • Journal of the Korean Society of Systems Engineering
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    • v.13 no.1
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    • pp.15-23
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    • 2017
  • This paper describes verification of APR1400 reactor vessel by applying the system engineering approach, in which the design re-engineering method is used to check the design parameters of APR1400 RV (reactor vessel). The RV is classified as safety class 1 and therefore must adhere strictly to the rules of ASME BPVC section III, subsection NB and seismic category I. This study explores designing the RV by following the ASME guidelines and making a comparative study with the current design. To meet this objective we apply system engineering methodologies to structure the process and allow for verification and validation of the major RV design parameters such as thickness of RV. The structural thicknesses of various part of RV are determined as well as reinforcements on the RV major nozzles. A 3D virtual reality model was created based on the design parameters using CATIA V5 and animation using Dassault Composer V2016. A comparison of re-engineered ARP1400 RV and standard APR1400 RV was done to show which design parameters were taken more conservative approach.

A Basic Study on the Extension of Design Information to Improve Interoperability in BIM-based Collaborative Design Process (BIM 기반 협업에서의 상호운용성 향상을 위한 설계정보의 확장방안에 대한 기초적 연구)

  • Jung, Jae-Hwan;Kim, Jim-Man;Kim, Sung-Ah
    • Journal of KIBIM
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    • v.5 no.1
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    • pp.25-34
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    • 2015
  • In the initial step of BIM based architectural design process, workloads are increased and the decision making process becomes more complex than those of the conventional design process. Technologies regarding distribution, exchange, classification, verification of BIM data are fundamental elements of construct environment for information sharing based on BIM. Interoperability of BIM model data is another issue to integrate BIM model. To improve interoperability in BIM-based collaboration, a model for utilizing formal&unformal design informations is suggested. Futhermore, Prototyping the model and practical test is conducted for advancement of data exchange making design data richen.

Optimization of Forging Process of Gate Valve using DACE Model (DACE 모델을 이용한 게이트밸브 단조공정의 최적설계화)

  • Oh, Seung-Hwan;Kong, Hyeong-Geol;Kang, Jung-Ho;Park, Young-Chul
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.6 no.1
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    • pp.71-77
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    • 2007
  • In case of the welding process, a conventional production method of gate valve, it has a merit of light weight, but also a demerit of high production cost and an impossibility in mass production due to work by hand. However, in case of the forging process, it has economic merits and can take a mass production process, too. The main focus of this paper is the optimization of preform in the forging process. This paper proposed an optimal design to improve the mechanical efficiency of gate valve made by forging method instead of welding. the optional design is conducted as application of real response model to Kriging model using computer simulation. Also, from verification of the response model with optimized results we were confirmed that the applications of Kriging method to structural optimum design using finite element analysis and equation are useful and reliable.

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LTS Semantics Model of Event-B Synchronization Control Flow Design Patterns

  • Peng, Han;Du, Chenglie;Rao, Lei;Liu, Zhouzhou
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.570-592
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    • 2019
  • The Event-B design pattern is an excellent way to quickly develop a formal model of the system. Researchers have proposed a number of Event-B design patterns, but they all lack formal behavior semantics. This makes the analysis, verification, and simulation of the behavior of the Event-B model very difficult, especially for the control-intensive systems. In this paper, we propose a novel method to transform the Event-B synchronous control flow design pattern into the labeled transition system (LTS) behavior model. Then we map the design pattern instantiation process of Event-B to the instantiation process of LTS model and get the LTS behavior semantic model of Event-B model of a multi-level complex control system. Finally, we verify the linear temporal logic behavior properties of the LTS model. The experimental results show that the analysis and simulation of system behavior become easier and the verification of the behavior properties of the system become convenient after the Event-B model is converted to the LTS model.