• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.39 no.3
• /
• pp.291-301
• /
• 2015

Product regulations specify requirements or constraints for products that manufacturers must comply with across the entire product lifecycle, from design and manufacture, through operation and maintenance, to recycling and disposal. This paper suggests a system framework and its essential components for the verification of a pressure vessel design using the industrial standards of Korea. The authors also present methods to generate design template data from legacy design systems and to construct a regulation knowledge base. The proposed framework is demonstrated through experiments involving pressure vessel design verification using a prototype system.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.117-120
• /
• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.345-348
• /
• 2001

The paper describes the physical design flow & verification of Digital Video Broadcasting(DVB) compliant satellite receiver chip. It includes problems and issues of earth design flow, verification process for physical layout.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.815-818
• /
• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.

• Proceedings of the Korean Nuclear Society Conference
• /
• 1998.05a
• /
• pp.335-340
• /
• 1998

In this paper a prototype of Requirement Tracking and Verification System(RTVS) for a Distributed Control System was implemented and tested. The RTVS is a software design and verification tool. The main functions required by the RTVS are managing, tracking and verification of the software requirements listed in the documentation of the DCS. The analysis of DCS software design procedures and inter(aces with documents were performed to define the user of the RTVS, and the design requirements for RTVS were developed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.83-88
• /
• 2007

In this paper, we propose the function verification method of the OLED(Organic Light Emitting Diode) drive IC using PLI verification method. This method uses the HDL(Hardware Description Language) simulator, PLI(Programing Language Interface), and GUI (Graphic User Interface) image viewer. This method improves the execute efficiency 40 times than conventional function verification methods. The proposed method can be used efficiently for function verification of DDI(display driver IC) design step.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.29 no.10 s.241
• /
• pp.1353-1360
• /
• 2005

Injection-molded products serve a wide range of applications in our modem lives and their significance is ever increasing. However, difficulty of communication among related companies under the present system results in increase of lead time and decrease of production efficiency. The objective of this paper is the development of a web-based draft verification system in mold design processes. Although several commercial CAD systems offer draft verification functions, those systems are very expensive and inadequate to perform collaborative works. For collaborative work under the distributed environment, the proposed system uses native file transforming of CAD data into optimal format by using the ACIS kernel and InterOp. Functions of draft verification modules are constructed over the ActiveX control using the visual C++ and OpenGL. Therefore, collaborators related to the development of a new product are able to verify the draft and undercut over the Internet without commercial CAD systems. The system helps to reduce production cost, errors and lead-time to the market. Performance of the system is confirmed through various case studies.

• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.659-664
• /
• 2008

The Railroad Safety Act's regulation reads as follows. "The Minister of Construction and Transportation may qualify and authorize the product to guarantee performance and safety of parts, machine, and device used in Railway fields." Another regulation reads as follows."“The guidelines about targets, standards, and procedures of Quality and Authority in first provision are decided as Ministry of Construction and Transportation Decree." The software used in rail cars and facilities is considered as a railway product. Therefore, it is qualified and authorized for acquiring the safety of rail cars and facilities. The software businesses shall again a Quality and Authority for applying a software to the rail cars and facilities. This paper regulates some guidelines that are needed to develop a software. The procedures that a software developer performs are divided by plan, requirement, design, implementation, and maintenance. The procedures that a software verification person performs are classified by verification plan, requirement verification, design verification, implementation verification, testing verification, maintenance verification, and safety activity. The entire processes and detailed activities to develope and verify a software are described as new guidelines.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.4
• /
• pp.309-314
• /
• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• 시스템엔지니어링워크숍
• /
• s.1
• /
• pp.9-14
• /
• 2003

The paper aims at presenting a systematic approach process and a method of requirement validation and system verification. Validation is applied during concept development to ensure conceptual validity, requirements validity, and design validity. Verification work is applied subsequent to the design work on test articles and early production items to produce evidence that the design solutions do, in fact, satisfy th requirements. In this paper, we present a requirements validation model and a system verification model. This models are applied to the development of TTX(Tilting Train Express)system with systems engineering tool, CORE.