• International Journal of Contents
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• 제7권1호
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• 제어로봇시스템학회논문지
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• 제14권8호
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• pp.824-836
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• 2008

Relaxed static stability(RSS) concept has been applied to improve aerodynamic performance of modern version supersonic jet fighter aircraft. Therefore, flight control systems are necessary to stabilize an unstable aircraft, and provides adequate handling qualities and achieve performance enhancements. Standard FCSDVP (Flight Control System Design and Verification Process) is provided to reduce development period of the flight control system. In addition, if this process is employed in developing flight control system, it reduces the trial and error for development and verification of flight control system. This paper addresses the flight control system design and verification process for the RSS aircraft utilizing design goal based on military specifications, linear and nonlinear system design and verification based on universal software, handling quality test based on HILS(Hardware In-the-Loop Simulator) environment, and ground and flight test results to verify aircraft dynamic flight responses.

• 대한전자공학회논문지SD
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• 제47권2호
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• pp.106-114
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• 2010

본 논문은 기가 스케일 System on Chip(SoC)를 위한 통합 설계 및 검증 플랫폼을 제안한다. VLSI 집적도의 발달로 그 복잡도가 증가하여 기존의 RTL 설계 방식으로는 그 생산성 차이(Production Gap)를 극복할 수 없게 되었다. 또한, 검증 차이(Verification Gap)의 증가로 검증 방법론에도 커다란 변혁이 필요하게 되었다. 본 플랫폼은 기존의 상위 수준 합성을 포함하며, 그 결과물을 이용하여 저 전력 설계의 전원 인식 검증 플랫폼과 검증 자동화를 개발하였다. 상위 수준 합성 시 사용되는 Control and Data Row Graph (CDFG)와 고 입력인 상위 수준 언어와 RTL를 기반으로 한 검증 플랫폼 자동화와 전원 인식 검증 방법론을 개발하였다. 검증 플랫폼에는 자동 검사 기능을 포함하고 있으며 Coverage Driven Verification을 채택하고 있다. 특히 전원 인식 검증을 위하여 개발된 조건 랜덤 벡터 생성 알고리듬을 사용하여 랜덤 벡터의 개수를 최소 5.75배 감소시키는 효과를 가져왔고, 전원과 전원 셀에 대한 모델링 기법을 이용하여 일반적인 로직 시뮬레이터 툴을 통해서도 전원 인식 검증을 가능하게 하였다. 이러한 통합된 설계 및 검증 플랫폼은 시스템 수준의 설계에서 검증, 합성에 이르는 전 설계 흐름을 완전 자동화 하여 상위 수준의 설계와 검증을 가능하게 하고 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.65-68
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• 2002

The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.939-942
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• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• 디지털산업정보학회논문지
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• 제7권2호
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• pp.29-37
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• 2011

Java bytecode verification is a critical process to guarantee the safety of transmitted Java applet on the web or contemporary embedded devices. We propose a design of framework which enables to analyze and verify java bytecode. The designed framework translates from a java bytecode into the intermediate representation which can specify a properties of program without using an operand stack. Using the framework is able to produce automatically error specifications that could be occurred in a program and express specifications annotated in intermediate representation by a user. Furthermore we design a verification condition generator which converts from an intermediate representation to a verification condition, a verification engine which verifies verification conditions from verification condition generator, and a result reporter which displays results of verification.

• 전자공학회지
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• 제30권9호
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• 대한기계학회논문집A
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• 제28권7호
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• pp.961-969
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• 2004

Most manufacturing companies are trying to develop a competitive product by increasing the quality, shortening time to market and reducing the cost of a product. Collaborators related to the development of a new product want to confirm geometric forms and dimensions during the design process, as well as to verify dimensional errors of a product during the fabrication process. Objective of this paper is the development of a collaborative design and dimension verification system on the Internet. STEP files obtained from the design process are used for the design and dimension verification. Functions of the design and dimension verification modules are constructed over the ActiveX control using the visual C/sup ++/ and OpenGL. By using mark up functions over the Internet, collaborators check geometries, interferences, dimensional errors, human factors and form errors, as well as share their design ideas and opinions with XML rapidly and remotely. The usefulness of the developed system is confirmed through case studies.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제8권3호
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• pp.261-267
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• 2002

SOC(System On a Chip)에 대한 설계에서 설계 생산성을 향상시키기 위해서 가장 시급히 해결해야 할 과제가 하드웨어뿐만 아니라 소프트웨어가지도 함께 동시검증(co-verification)하여야 함으로서 설계검증에 과도하게 투입되는 비용과 시간을 줄이는 것이다. 본 논문에서는 이러한 설계검증 생산성을 효과적으로 높이기 위한 방법으로 HW/SW 동시검증을 수행할 수 있는 대표적인 두 방법들인 동시-시뮬레이션(co-simulation)과 동시-에뮬레이션(co-emulation)을 강하게 결합한 새로운 검증 방법인 집적 동시검증(integrated co-verification) 방법을 제안하였다. 또한, 상용화된 동시검증 툴인 Seamless CVE와 물리적 프로토타이핑 보드를 함께 사용하여 구성한 ARM/AMBA 플랫폼 기반의 집적 동시검증 환경을 직접 구성하고, 이를 이용하여 제안된 검증기법의 유용성을 실험적으로 확인하였다.

• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.