• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.215-223
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• 2003

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GFP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, l/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and denveloped the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1575-1579
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• 1999

Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• 한국신재생에너지학회:학술대회논문집
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• 2008.10a
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• pp.303-306
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• 2008

This study proposes an essential process of type certificate, which is load comparison for proving the calculated design load. The load measurement was carried out according to IEC 61400-13 standard and the load calculation was performed with same condition using FLEX 5 code. For more accurate load simulation, the controller parameter of original model at the design stage was modified to site optimized value and some node points are added to coincidence with measurement. The load comparison was performed with various wind parameter, turbulence intensity and wind shear. As a result, simulated loads ware good agreed with the measured load. Therefore, the calculated design loads according to IEC 61400-1 standard were proved to valid.

• International Journal of High-Rise Buildings
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• v.2 no.3
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• pp.257-269
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• 2013

This study presents the development of an advanced multiple database-enabled design module for high-rise buildings (DEDM-HR), which seamlessly pools databases of multiple high frequency base balance measurements from geographically dispersed locations and merges them together to expand the number of available building configurations for the preliminary design. This feature offers a new direction for the research and professional communities that can be utilized to efficiently pool multiple databases therefore expanding the capability of an individual database and improving the reliability of design estimates. This is demonstrated, in this study, by the unprecedented fusion of two major established databases, which facilitates interoperability. The DEDM-HR employs a cyberbased on-line framework designed with user-friendly/intuitive web interfaces for the convenient estimation of wind-induced responses in the alongwind, acrosswind and torsional directions with minimal user input. In addition, the DEDM-HR embeds a novel feature that allows the use of wind characteristics defined in a code/standard to be used in conjunction with the database. This supplements the provisions of a specific code/standard as in many cases guidance on the acrosswind and torsional response estimates is lacking. Through an example, results from several international codes and standards and the DEDM-HR with the embedded features are compared. This provision enhances the scope of the DEDM-HR in providing an alternative design tool with nested general provisions of various international codes and standards.

• Steel and Composite Structures
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• v.38 no.2
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• pp.121-139
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• 2021

Ultra-high strength concrete (UHSC) encased steel columns are receiving growing interest in high-rise buildings owing to their economic and architectural advantages. However, UHSC encased steel columns are not covered by the modern fire safety design code. A total of 14 fire tests are conducted on UHSC (120 MPa) encased steel columns under constant axial loads and exposed to ISO-834 standard fire. The effect of load ratio, slenderness, stirrup spacing, cross-section size and concrete cover to core steel on the fire resistance and failure mode of the specimens are investigated. The applicability of the tabulated method in EC4 (EN 1994-1-2-2005) and regression formula in Chinese code (DBJ/T 15-81-2011) to fire resistance of UHSC encased steel columns are checked. Generally, the test results reveal that the vertical displacement-heating time curves can be divided into two phases, i.e. thermal expansion and shortening to failure. It is found that the fire resistance of column specimens increases with the increase of the cross-section size and concrete cover to core steel, but decreases with the increase of the load ratio and slenderness. The EC4 method overestimates the fire resistance up to 186% (220 min), while the Chinese code underestimates it down to 49%. The Chinese code has a better agreement than EC4 with the test results since the former considers the effect of the load ratio, slenderness, cross section size directly in its empirical formula. To estimate the fire resistance precisely can improve the economy of structural fire design of ultra-high strength concrete encased steel columns.

• Journal of the Korean Society of Safety
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• v.21 no.6 s.78
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• pp.20-25
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• 2006

In the design of class 1 components to apply ASME code section III NB, a fatigue is considered as one of the important failure mechanisms. Fatigue analysis procedure and standard fatigue design curve(S-N curve) is suggested in ASME code, which had to be performed to meet the integrity of components at the design step. As the plant life extension for operating power plants and the long-lived plant design, however, are being progressed, the fact which the existing ASME fatigue design curve can not consider fatigue effects sufficiently comes to the fore. To find the technical solution for these problems, a number of researches and discussion are continued up to now. In this study, the detailed fatigue analyses using the 3 dimensional modeling for the fatigue-weakened components were performed to develop the optimized fatigue analysis procedure and their results are compared with other reference solutions.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.365-368
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• 2003

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.443-445
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• 2006

In this paper, we present a model-driven approach to RTOS(Real Time Operating System)-based embedded software development and an automated tool that can produce RTOS-specific code. we defined generic RTOS APIs(Application Programming Interface) that are not bound to any specific RTOS but can provide most of typical RTOS services. The generic RTOS APIs can be used as a means for describing application's RTOS-related behavior from design stage. Out tool, called Trans-PI, is able to produce specific 'C' code aimed at POSIX(Portable Operating System Interface for UNIX)-complicant RTOSs. And it is also configurable to target other RTOSs that do not conform to the POSIX standard.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.818-830
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• 2000

Automation tools for program analysis are needed in order to program understand and maintain, extract the characteristics of object-oriented program such as class name, member function and data member. In this paper, we carried out design and implementation of the automation tool for effective maintenance of object-oriented software. Being based on Reverse Engineering, this approach extracts class relationship information from C++ source code and generates object-oriented model of class diagram using UML as the standard object-oriented methodology. Therefore, this paper provides developers visualized including class information, definitions of classes, inheritance relationships, set relationships, and simple reference relationships. Finally in this paper, we propose a method that construct class relationship information to table in analysis state and make form of table construction to link form so tat developers can perform understanding and maintaining program efficiently. And this method enable to restructure and reuse in object-oriented model.