• Title/Summary/Keyword: Design Speed

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Studies on the Structural Design of Biological Production Facility I. Frequency Analysis of Weather Data for Design Load Estimation (생물생산시설의 구조설계에 관한 연구 I. 설계하중 산정을 위한 기상자료 빈도분석)

  • 김문기;손정익;남상운;이동근;이석재
    • Journal of Bio-Environment Control
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    • v.1 no.1
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    • pp.1-13
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    • 1992
  • This study was attemped to provide some fundamental data for the safety structural design of biological production facility. Wind speed and snow depth according to recurrence intervals for design load estimation were calculated by frequency analysis using the weather data of 60 stations in Korea. The following results were obtained : 1. Type-I extremal distribution was selected for the probability density function of yearly maximum wind speed and snow depth and result of Chi-square goodness of fit showed highly significance at most regions. 2. Design frequency factors for given number of samples and recurrence intervals were calculated, and also design wind speed and snow depth as shown in Table 5-Table 6 and Fig.3-Fig.4 were derived. 3. About 46.4% of the winds having maximum wind speed at every station was analyzed to be same direction, and the consideration of this fact may improve the structural safety. 4. Considering wind speed and snow depth, protected cultivation is very difficult in Ullungdo and the Youngdong districts, and strong structural design is needed in the Chungnam and Junbuk west seaside against snow depth and the west-south seaside against wind speed in Korea.

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The Scenary Design for the Service car of High Speed Train (고속전철 부속실 풍경 디자인)

  • 한송이;이선영;최혁수;이병종;정경렬
    • Proceedings of the Korea Society of Design Studies Conference
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    • 2000.11a
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    • pp.84-85
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    • 2000
  • G7 고속전철개발 산업에서 계획된 부속실은 경부 고속전철(K-TGV)의 부속실을 그대로 사용하는 것으로서 좁은 통로와 획일적 공간, 불필요한 공간에 의한 승객 편의시설의 결여되었기에, 이의 수정보완이 요구되었다. 아래의 사진들은 K-TGV의 부속실 모습이다. (중략)

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Speed Control ASIC Design of Induction Motor (VHDL을 이용한 유도전동기의 속도제어 ASIC 설계)

  • Park, H.J.;Kim, C.H.;Kwon, Y.A.
    • Proceedings of the KIEE Conference
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    • 1999.07f
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    • pp.2758-2760
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    • 1999
  • ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

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Design and Implementation of Backplane for High Speed Router (고속라우터용 백플레인 설계 및 구현)

  • 이상우;이강복;이형섭;이형호
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.275-278
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    • 2000
  • As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

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A new design of the SCR type speed controller for the battery powered electric vehicles (SCR을 이용한 전기자동차의 속도제어장치의 설계와 시작)

  • 황희융
    • 전기의세계
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    • v.24 no.6
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    • pp.85-91
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    • 1975
  • A new design method for the SCR-Chopper type speed controller of the battery-powered vehicles was developed. The conventional speed-controllers were either inductance type or contact type using resistance. In the new method, a photocoupler was used in sensing the control currents and a noncontacting type photo-conductive device (CDS) was used in mading acceleration. Experiments using these new devices showed encouraging results.

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The Design and the Characteristics of SRM Drive for Low Speed Vehicle (LSEV용 SRM의 설계 및 구동특성)

  • Kim, C.S.;Oh, S.G.;Ahn, J.W.;Hwang, Y.M.
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.871-873
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    • 2001
  • The switched reluctance motor (SRM) is gaining much interest as a candidate for electric vehicle for its simple and rugged construction, ability of extremely high-speed operation. This paper is to design and investigate the capabilities of the SRM for low speed electric vehicle (LSEV).

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The Design, Fabrication and Characteristic Experiment of Rotational Speed Sensor for SMART Main Coolant Pump (일체형원자로 냉각재순환펌프용 회전속도측정기 설계 및 특성시험)

  • Huh, Hyung;Kim, Jong-In;Kim, Kern-Jung
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.774-776
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    • 2001
  • This paper describes the finite element analysis(FEA) for the design of common core-type and separated core-type rotational speed sensor(RSS) for SMART MCP and compared with the low/ high speed characteristics of prototype RSS. As a result, it is shown that the characteristics of prototype RSS have a good agreement with the results of FEA.

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A Study on the optimal Size and Speed of Common Bulk Carrier (일반살화물선의 경제성 평가에 관한 연구 (속력 및 적화톤수를 중심으로))

  • 양시권;손성빈
    • Journal of the Korean Institute of Navigation
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    • v.6 no.1
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    • pp.19-39
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    • 1982
  • There may be a lor of studies on the economic design of ship for the most favorable combination of design basis on the owner's request. However, there are few on the economical ship's size and speed for the ship owner's stand point. This paper describes on the optimal ship's size and speed to the given marine commercial environments for the owner's requirement to the shipyard. As the result of the paper, the criterion curve of bulk carrier will also be used to assess existing ships for their profitability.

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A variable-speed deburring robot using the repetitive control

  • Kimura, Yoichi;Mukai, Ryoji;Kobayashi, Fuminori
    • 제어로봇시스템학회:학술대회논문집
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    • 1989.10a
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    • pp.663-668
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    • 1989
  • Control methods to achieve efficient and accurate deburring robots are proposed. For efficiency, cutting speed is controlled adoptively with the cutting load. For accuracy, it adopts repetitive control. Since usual repetitive control cannot afford dynamical speed changes, the proposed method controls in an interpolating manner using several waveforms stored in the controller. Successful experimental results axe shown.

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A 6bit 800MSample/s A/D Converter Design for Hard Disk Drive Read Channel (하드디스크 드라이브 읽기 채널용 6bit 800MSample/s 아날로그/디지털 변환기의 설계)

  • 정대영;장흥석;신경민;정강민
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.164-167
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    • 2000
  • This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

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