• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.57-62
• /
• 2009

In this paper, to implement PCS (Physical Coding Sublayer) of 10GBASE-R type, we present 2 stage pipeline 64b/66b Encoder/Decoder which operates at 156.25MHz standard specification and designed to minimize clock latency as possible as we can. The proposed circuit was designed based on Verilog hardware description language and measured for functional verification on VertexII-1000fg456 chip of Xilinx Inc.. Total equivalent gate count is 47,303 and estimated power consumption is 351mW at Vcc 3.3V.

• Journal of Communications and Networks
• /
• v.12 no.6
• /
• pp.558-567
• /
• 2010

In this paper, we analyze the capability of satellite broadcasting systems to offer different levels of quality of service (QoS). We focus on the European telecommunications standards institute satellite digital radio and digital video broadcasting satellite handheld (DVB-SH) standards, which have recently been proposed for satellite broadcasting communications. We propose a strategy to provide different levels of QoS for the DVB-SH standard on the basis of an extension of the interleaving scheme, referred to as molded interleaver, which supports low latency service requirements for interactive services. An extensive analysis based on laboratory measurements shows the benefits of this solution. We also present a multilevel coding (MLC) scheme with multistage decoding designed for broadcasting communications as an alternative to the existing standards, where services with different levels of QoS are provided. We present a graphical method based on mutual information for the design and evaluation of MLC systems used for broadcasting communications. Extensive simulations for a typical satellite channel show the viability of the proposed MLC scheme. Finally, we introduce multidimensional constellations in the proposed MLC scheme in order to increase the number of different protection levels.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2005.11a
• /
• pp.209-212
• /
• 2005

This paper introduces interactive multi-view contents authoring system based on MPEG-4. The MPEG-4 standard, which aims to provide an object based audiovisual coding tool, has been developed to address the emerging needs from communications, interactive broadcasting as well as from mixed service models resulting from technological convergence. Due to the feature of object based coding, it has been considered that MPEG-4 is the most suitable for interactive broadcasting content production. This feature is suitable for creation of the content which provides multiple views of object or scene in interactive manner. In this paper, we categorize the multi-view visual content into two types: panoramic multi-view content and object multi-view content. And design and implementation of the authoring system for interactive multi-view contents is presented. We believe that the proposed method can be effectively used for further deployment of MPEG-4 content to various interactive applications.

• Journal of Practical Engineering Education
• /
• v.16 no.2
• /
• pp.151-157
• /
• 2024

Most of the existing game-based education programmes for lower grades are simple block-coding studies, and there is a lack of examples of programming-intensive classes. In this study, we implemented a Minecraft-based Python coding fundamentals class for 3 classes at a local elementary school during a 2-week school holiday. The learning programme was reorganised from the standard learning programme on the official website, such as building quests through LAN-PARTY and self-scripting in-game, to improve class interest and motivation. In addition, we analysed the satisfaction and preferences of the class topics through a survey, and obtained meaningful results for future educational program development. This study is significant as a basic research for the design and development of game-based educational programmes for all age groups.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.5
• /
• pp.335-344
• /
• 2003

The image compression based on discrete wavelet transform has been widely accepted in industry since it shows no block artifacts and provides a better image quality when compressed to low bits per pixel, compared to the traditional JPEG. The coefficients generated by discrete wavelet transform are quantized to reduce the number of code bits to represent them. After quantization, lossless coding processes are usually applied to make further reduction. This paper presents a new and efficient lossless coding algorithm for quantified wavelet coefficients based on the statistical properties of the coefficients. Combined with discrete wavelet transform and quantization processes, our algorithm has been implemented as an image compression chip, using 0.5${\mu}{\textrm}{m}$ standard cells. The experimental results show the efficiency and performance of the resulting chip.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.3
• /
• pp.585-593
• /
• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.45-53
• /
• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Transactions on Electrical and Electronic Materials
• /
• v.13 no.5
• /
• pp.256-261
• /
• 2012

Recently, many photovoltaic systems (PV systems) including solar parks and PV farms have been built to prepare for the post fossil fuel era. To investigate the degradation process of the PV systems and thus, efficiently operate PV systems, there is a need to visually monitor PV systems in the range of infrared ray through the Internet. For efficient visual monitoring, this paper explores a multithreaded implementation of a recently developed HEVC standard whose compression efficiency is almost two times higher than H.264. For an efficient parallel implementation under a meshbased 64 multicore system, this work takes into account various design choices which can solve potential problems of a two-dimensional interconnects-based 64 multicore system. These problems may have not occurred in a small-scale multicore system based on a simple bus network. Through extensive evaluation, this paper shows that, for an efficient multithreaded implementation of HEVC intra prediction in a mesh-based multicore system, much effort needs to be made to optimize communications among processing cores. Thus, this work provides three design choices regarding communications, i.e., main thread core location, cache home policy, and maximum coding unit size. These design choices are shown to improve the overall parallel performance of the HEVC intra prediction algorithm by up to 42%, achieving a 7 times higher speed-up.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2014.06a
• /
• pp.160-162
• /
• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• Proceedings of the Korea Contents Association Conference
• /
• 2003.11a
• /
• pp.113-119
• /
• 2003

Both the highly developed computing environment and the rapid increase of the internet users enable the present web based cluster system accounting service to help many users access to numerous data at high speed. However, the information security of users and data is also as important as the convenience of the systematic environment. Especially, the significance of damage to the individuals and organizations resulted from the data outflow, hacking and malicious coding has risen up to one of the most essential problems in the internet service business. In this study, I suggest a more safe web based cluster system accounting service solution applying SEED, the Korean Telecommunications Technology Association (TTA) standard encryption algorithm.