• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.79-82
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• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2043-2054
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• 1996

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of Positioning, Navigation, and Timing
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• v.1 no.1
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• pp.1-6
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• 2012

For a Global Positioning System (GPS) receiver, it is known that a Vector Delay Locked Loop (DLL) in which the code signals of each satellite are tracked in parallel by using navigation results shows better performance in the aspect of the tracking accuracy and the robustness than that of a Scalar DLL. However, the quantitative analysis and the logical grounds for that performance enhancement of the Vector DLL are not sufficient. This paper, therefore, proposes the structure of the GPS receiver with the Vector DLL and analyzes the performance of it. The tracking and the positioning accuracy of the Vector DLL are theoretically analyzed and confirmed by simulation results. From the simulation results, it can be seen that the tracking and positioning accuracy has been improved about 30% in case that the receiver is static and the positioning is conducted for every Pre-detection Integration Time (PIT) while C/N0 is 45 dB-Hz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.55-64
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• 1997

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL, Tau-dither, SO etc, in the synchronous method. But since there are analog operations, the settling is difficult and size is large. In this paper we realized Digital Delay Lock Loop (DDLL) and estimated it's performance through the Power line experiment.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.