• 반도체디스플레이기술학회지
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• 제2권3호
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• pp.7-11
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• 2003

In this research, the etching characteristics of via contact and deep contact hole have been studied using multi-pole inductively coupled plasma(MICP) etching system. We investigated Plasma density of MICP source using the Langmuir probe and etching characteristics with RF frequency, wall temperature, chamber gap, and gas chemistry containing Carbon and Fluorine. As the etching time increases, formation of the polymer increases. To improve the polymer formation, we controlled the temperature of the reacting chamber, and we found that temperature of the chamber was very effective to decrease the polymer thickness. The deep contact etch profile and high selectivity(oxide to photoresist) have been achieved with the optimum mixed gas ratio containing C and F and the temperature control of the etching chamber.

• 한국세라믹학회지
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• 제39권6호
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• pp.570-575
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• 2002

현재 전기 . 전자 기술의 추세는 소형화를 비롯하여 집적화, 저전력화, 저가격화의 장점을 가진 MEMS(Micro Electro Mechanical Systems) device의 개발에 주력하고 있으며, 이를 위해서는 고종횡비와 높은 식각 속도를 가진 HDP(High Density Plasma) etching 기술 개발이 필수적이라 할 수 있다. 이를 위하여 우리는 Inductively Coupled Plasma(ICP) 장비를 이용하여 각 공정 변수에 의한 실리콘 deep trench식각 반응을 연구하였다. 실험 공정 변수인 platen power, etch/passivation cycle time에서 etching 단계 시간에 따른 변화와 SF$_{6}$:C$_4$F$_{8}$ 가스유량을 변화시켜 연구하였으며 또한 이들의 profile, scallops, 식각 속도, 균일도, 선택비도 관찰하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.118-119
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• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• 전기학회논문지
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• 제56권12호
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• pp.2221-2225
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• 2007

Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.701-707
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• 2004

High aspect ratio silicon structure through deep silicon etching process have become indispensable for advanced MEMS applications. In this paper, we present the results of modified Bosch process to obtain anisotropic silicon structure with conventional Inductively Coupled Plasma (ICP) etcher instead of the expensive Bosch process systems. In modified Bosch process, etching step ($SFsub6$) / sidewall passivation ($Csub4Fsub8$) step time is much longer than commercialized Bosch scheme and process transition time is introduced between process steps to improve gas switching and RF power delivery efficiency. To optimize process parameters, etching ($SFsub6$) / sidewall passivation ($Csub4Fsub8$) time and ion energy effects on etching profile was investigated. Etch profile strongly depends on the period of etch / passivation and ion energy. Furthermore, substrate temperature during etching process was found to be an important parameter determining etching profile. Test structures with different pattern size have been etched for the comparison of the aspect ratio dependent etch rate and the formation of silicon grass. At optimized process condition, micropatterns etched with modified Bosch process showed nearly vertical sidewall and no silicon grass formation with etch rate of 1.2 ${\mu}{\textrm}{m}$/ min and the size of scallop of 250 nm.

• 센서학회지
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• 제24권1호
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• 한국산학기술학회논문지
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• 제5권2호
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• pp.128-131
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• 2004

본 연구에서는 STS-ICP ASEHR을 이용하여 Etch와 Deposition 공정을 반복하여 에칭을 하는 Bosch 식각에 관하여 연구하였다. 기본적인 Etch rate의 변화는 Etching하고자 하는 Wafer에 Deposition된 PR 또는 SiO₂의 두께와 Etching하고자 하는 Wafer의 Depth 및 Pattern size가 영향을 준다. 그러나 이러한 기본적인 변수 외에 STS-ICP ASEHR 장비의 Platen power, Coil power 및 Process pressure에 다양한 변화를 주어 각 변수에 따른 Etch rate을 관찰하였다. 각 공정별 변수를 준 결과 Platen power 12W, Coil power 500W, Etch/Passivation Cycle 6/7sec 일 경우 Etch rate은 1.2㎛/min 이었고, Sidewall prpfile은 90±0.2˚로 나타나 매우 우수한 결과를 보였다. 이는 ICP를 이용한 Bosch Process에 의한 결과임을 확인할 수 있었다.

• Applied Microscopy
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• 제28권1호
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• pp.73-82
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• 1998

본 연구에서는 급속동결 deep etching법을 이용하여 흰쥐에서 담세관주위세포질에 있는 미세사와 용해소체 및 소포등 세포내소기관들이 어떻게 담즙분비에 관여하는지를 알아 보고자 하였다. Taurocholic acid를 투여한 군은 정상군에 있어서와 같이 미세사가 담세관 주위를 둘러싸면서 담세관 원형질막과 다른 세포내소기관에 부착되어 있었다. 이들 담세관 주위의 미세사들은 미세융모속에서 다발을 이루고 있었으며 담세관 둘레에서는 관주위직을 형성하면서 연접복합체에 결합되어 있었다. 미세사는 또한 담세관 원형질막과 소포사이에 걸쳐있는 것도 관찰되었다. 이상의 소견으로 미루어 미세사는 담세관에서의 담즙의 분비를 돕는 소기관임을 알 수 있는데 특히 담세관에 융합할 수 있도록 소포의 전위를 유도하는 기구로서 작용할 것으로 추정된다.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 추계학술대회 발표 논문집
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• pp.198-201
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• 2006

In this paper, we fabricated drag force type and pressure difference type gas flow sensor with dry etching technology which used Deep RIE(reactive ion etching) and etching stop technology which used SOI(silicon-on-insulator). we fabricated four kinds of sensor, which are cantilever, paddle type, diaphragm, and diaphragm with orifice type. Both cantilever and paddle type flow sensors have similar sensitivity as 0.03mV/V kPa. Sensitivity of the fabricated diaphragm and diaphragm with orifice type sensor were relatively high as about 3.5mV/V kPa, 1.5mV/V kPa respectively.

• 대한전자공학회논문지SD
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• 제48권1호
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• pp.1-6
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• 2011

본 논문에서는 미세피치 프로브 카드 제작을 위한 S 모양의 일체형 외팔보 프로브 형성방법에 대하여 기술하였다. 마세 피치 프로브를 위하여 Deep RIE etching을 이용하여 실리콘 트렌치 안에 일체형 프로브 빔과 탑을 형성하는 방법을 사용하였고, 피라미드 팁의 형성을 위하여 KOH 및 TMAH 습식식각을 이용하였으며, 습식식각시 방향성을 가지는 실리콘 웨이퍼에서도 휘어진 형태의 프로브 빔을 형성할 수 있는 건식 식각 및 습식식각 방법을 제시하였다. 따라서 제작된 외팔보 형태의 프로브는 디렘(DRAM), 플레시 메모리 (Flash memory) 용 프로브 카드 제작에 사용될 뿐만 아니라 RF 소자용 프로브 카드, 아이씨 테스트 소켓 (IC test socket)용 프로브 탐침에도 사용 될 것이다.