• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.595-598
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• 2005

MPEG-4 Visual is, and international standard for the object-based video compression, designed for supporting a wide range of applications from multimedia communication to HDTV. To control the minimum decoding complexity required at the decoder, the MPEG-4 Visual standard defines the co-called video buffering mechanism, which includes three video buffer models. Among them, the VCV(Video Complexity Verifier) defines the control of the processing speed for decoding of a macroblock, there are two models: VCV and B-VCV distinguishing the boundary and non-boundary MB. This paper presents the evaluation results of decoding complexity by measuring decoding time of a MB for rectangular, arbitrarily shaped video objects and the various types of objects supporting the resolution of HDTV using the optimized MPEG-4 Reference Software. The experimental results shows that decoding complexity varies depending on the coding type and more effective usage of decoding resources may be possible.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.9-14
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• 2009

Recently, a rate-2, $2{\times}2$ space-time code with simple ML decoding has been designed. Though the simple ML decoding algorithm does reduce the ML decoding complexity, there is still need for improvement. In this paper, we propose an efficient decoding algorithm for the rate-2, $2{\times}2$ space-time code using interference cancellation techniques with performance virtually identical to that of ML decoding. Also, the decoding complexity of the proposed algorithm is significantly reduced compared to the conventional simple ML decoding, especially for large modulation orders.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.16-33
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• 1993

New decoding algorithm of double-error-correction Reed-Solmon codes over GF(2$^{8}$) for optical compact disks is proposed and decoding algorithm of RS codes with triple-error-correcting capability is presented in this paper. First of all. efficient algorithms for estimating the number of errors in the received code words are presented. The most complex circuits in the RS decoder are parts for soving the error-location numbers from error-location polynomial, so the complexity of those circuits has a great influence on overall decoder complexity. One of the most known algorithm for searching the error-location number is Chien's method, in which all the elements of GF(2$^{m}$) are substituted into the error-location polynomial and the error-location number can be found as the elements satisfying the error-location polynomial. But Chien's scheme needs another 1 frame delay in the decoder, which reduces decoding speed as well as require more stroage circuits for the received ocode symbols. The ther is Polkinghorn method, in which the roots can be resolved directly by solving the error-location polynomial. Bur this method needs additional ROM (readonly memory) for storing tthe roots of the all possible coefficients of error-location polynomial or much more complex cicuit. Simple, efficient, and high speed method for solving the error-location number and decoding algorithm of double-error correction RS codes which reudce considerably the complexity of decoder are proposed by using Hilbert theorems in this paper. And the performance of the proposed decoding algorithm is compared with that of conventional decoding algorithms. As a result of comparison, the proposed decoding algorithm is superior to the conventional decoding algorithm with respect to decoding delay and decoder complexity. And decoding algorithm of RS codes with triple-error-correcting capability is presented, which is suitable for error-correction in digital audio tape, also.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.12-18
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• 1993

We have proposed a soft-decision decoding method for block codes. With careful examinations of the first hard-decision decoded results, The candidate codewords are efficiently searched for. Thus, we can reduce the decoding complexity (the number of hard-decision decodings) and lower the block error probability. Computer simulation results are presented for the (23,12) Golay code. They show that the decoding complexity is considerably reduced and the block error probability is close to that of the maximum likelihood decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.329-336
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• 2010

Distributed source coding (DSC) system moves computational burden from encoder to decoder, so it takes higher decoding complexity. This paper explores the problem of reducing the decoding complexity of practical Slepian-Wolf coding using low-density parity check accumulate (LDPCA) codes. It is shown that the convergence of mean magnitude (CMM) stopping criteria for LDPC codes help reduce the 85% of decoding complexity under the 2% of compression rate loss, and marginal initial rate request reduces complexity below complexity minimum bound. Moreover, inter-rate stopping criterion, modified for rate-adaptable characteristic, is proposed for LDPCA codes, and it makes decoder perform less iterative decoding than normal stopping criterion does when channel characteristic is unknown.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.