• 정보처리학회논문지C
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• 제10C권1호
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• pp.27-32
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• 2003

본 논문에서는 선형 블록 부호에 대한 효율적인 연판정 복호법을 제안하였다. 제안된 연판정 복호법은 연판정 복호 과정을 반복하여 실현하는 방식이다. 경판정 복호 결과로부터 후보 부호버들을 효율적으로 탐색할 수 있는 방법을 개발하였다. 이 과정에서 후보 부호어가 선출되지 않는 경우의 발생을 억제할 수 있는 새로운 복호법을 제안하였다. 또한, 복잡도를 줄이는 방안도 개발하여 알고리듬 개선으로 인한 복잡도 증가가 거의 나타나지 않도록 하였다. 2진(63, 36) BCH 부호에 대한 시뮬레이션 결과로 이러한 사실들을 확인할 수 있었다.

• 대한전자공학회논문지TC
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• 제46권3호
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• pp.9-14
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• 2009

최근에 간단한 ML 복호가 가능한 rate-2, $2{\times}2$ 시공간 부호가 개발되었다. 비록 이러한 간단한 ML 복호 알고리즘이 ML 복호 복잡도를 줄여 주지만 여전히 향상될 여지가 남아 있다. 본 논문에서는 간섭제거 방법을 사용하여 ML 복호와 거의 동일한 성능을 가지면서 rate-2, $2{\times}2$ 시공간 부호를 위한 효율적인 복호 알고리즘을 제안한다. 제안된 알고리즘의 복호 복잡도는 기존의 간단한 ML 복호에 비해서도 더욱 감소하며 변조 차수가 클수록 복호 복잡도 감소율은 더욱 증가한다.

• 한국통신학회논문지
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• 제17권12호
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• pp.1401-1412
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• 1992

TCM(Trellis Coded Modulation)은 위성통신이나 음성통신과 같이 대역폭이 제한된 채널에서 코딩과 변조가 결합되어 대역폭의 증가없이 코딩 이득을 가져올수 있는 하나의 통신 방식이다. 본 논문에서는 PAM, PSK, QAM 변조를 TCM에 적용하고, Viterbi decoding의 단점을 개선할수 있는 확장된 path back method 복호 알고리즘을 제안하여 TCM의 복호 알고리즘에 적용하였다. 또한, Monte Carlo simulation을 이용하여 각 변조기법에 따른 성능과 복호 효율성에 대하여 분석하였다.

• 한국통신학회논문지
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• 제30권6C호
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

• IEIE Transactions on Smart Processing and Computing
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• 제6권3호
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• 전자공학회논문지A
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• 제30A권11호
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• pp.21-28
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• 1993

Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

• Journal of Communications and Networks
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• 제17권3호
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• Journal of applied mathematics & informatics
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• 제32권1_2호
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• pp.83-98
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• 2014

We reformulate an interpolation-based unique decoding algorithm of AG codes, using the theory of Gr$\ddot{o}$bner bases of modules on the coordinate ring of the base curve. The conceptual description of the reformulated algorithm lets us better understand the majority voting procedure, which is central in the interpolation-based unique decoding. Moreover the smaller Gr$\ddot{o}$bner bases imply smaller space and time complexity of the algorithm.

• Journal of applied mathematics & informatics
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• 제31권5_6호
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• pp.785-794
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• 2013

Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

• Journal of Communications and Networks
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• 제17권4호
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.