• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.27-32
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• 2003

An efficient soft-decision decoding algorithm for binary block codes it proposed. The proposed soft-decision decoding algorithm is implemented by a series of hard-decision decoding process. By the hard-decision decoding result, the candidate codewords are efficiently searched for A new decoding method, which prevents the missing of the candidate codeword, is proposed. Also, the method fir reducing complexity is developed. This method removes the practical complexity increase caused by the improved algorithm. There facts are confirmed by the simulation results for binary (63, 36) BCH code.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.9-14
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• 2009

Recently, a rate-2, $2{\times}2$ space-time code with simple ML decoding has been designed. Though the simple ML decoding algorithm does reduce the ML decoding complexity, there is still need for improvement. In this paper, we propose an efficient decoding algorithm for the rate-2, $2{\times}2$ space-time code using interference cancellation techniques with performance virtually identical to that of ML decoding. Also, the decoding complexity of the proposed algorithm is significantly reduced compared to the conventional simple ML decoding, especially for large modulation orders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1401-1412
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• 1992

On band limited channel like satellite communication and voice communication. TCM(Trellis Coded Modulation) is a communication method that has coding gain which combines modulation with channel coding without bandwidth expansion. In this paper, we apply PAM, PSK, QAM to TCM, and propose the extended path back method decoding algorithm which improved drawback of viterbi decoding algorithm and apply to TCM this decoding algorithm. Using Monte Carlo simulation, we analyze performance of each modulation technique and efficiency of decoding algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.21-28
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• 1993

Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• Journal of applied mathematics & informatics
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• v.32 no.1_2
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• pp.83-98
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• 2014

We reformulate an interpolation-based unique decoding algorithm of AG codes, using the theory of Gr$\ddot{o}$bner bases of modules on the coordinate ring of the base curve. The conceptual description of the reformulated algorithm lets us better understand the majority voting procedure, which is central in the interpolation-based unique decoding. Moreover the smaller Gr$\ddot{o}$bner bases imply smaller space and time complexity of the algorithm.

• Journal of applied mathematics & informatics
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• v.31 no.5_6
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• pp.785-794
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• 2013

Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.