• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.747-752
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• 1996

In this paper, we propose a new SO-MLSE(soft-output maximum likelihood sequence estimation) equalizer, which can be used in GSM digital cellular system) it uses complex correlation of training sequence to obtain the channel information and the equalization is performed by MLSE using Viterbi algorithm. In order to generate a soft-decision input to channel decoder (Viterbi decoder), the soft-output equalization algorithm is needed. The adopted algorithm doesn't require to modify the structure of HO-MLSE(hard output MLSE) equalizer, that is, SO-MLSE equalizer can be implemented by adding soft-output generation block to HO-MLSE equalizer. This algorithm uses the outputs of matched filter and HO-MLSE equalizer. It turns out that the complexity of proposed SO-MLSE equalizer is simpler than those of other SO-MLSE equalizer and its perforance is almost the same as those of others. Finally, the proposed SO-MLSE equalizer is also implemented s a prototype with ADSP-2101 16-bits fixed point digital signal processing chip.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.27-36
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• 1996

It is well known that the viterbi algorithm proposed as a mthod of decoding convolutional codes is in fact maximum likelihood (ML) and therefore optimal. But, because hardware complexity grows exponentially with the constraint length, there will be severe constraints on the implementation of the viterbi decoders. In this paper, the three-layered backpropagation neural networks are proposed as an alternative in order to get sufficiently useful performance and deal successfully with the problems of the viterbi decoder. This paper shows that the neural convolutional decoder (NCD) can make a decision in the point of ML in decoding and describes simulation results. The cause of the difference between stochastic results and simulation results is discussed, and then thefuture prospect of the NCD is described on the basis of the characteristic of the transfer function.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.299-304
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• 2008

For perpendicular magnetic recording channels, it is hard to expect improving the performance by using the PRML or NPML. Hence, we exploit LDPC code to improve the performance. In this paper, we examine a single message-passing detector/decoder matched to the combination of a perpendicular magnetic recording channel detector and an LDPC code decoder. We examine the performance of channel iteration with joint LDPC code on perpendicular magnetic recording channel, and simplify the complexity of the message-passing detector algorithm.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.463-471
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• 2019

This paper proposes a method for reducing the complexity of LIC (Local Illuminance Compensation) for bi-directional inter prediction. The LIC performs local illumination compensation using neighboring reconstruction samples of the current block and the reference block to improve the accuracy of the inter prediction. Since the weight and offset required for local illumination compensation are calculated at both sides of the encoder and decoder using the reconstructed samples, there is an advantage that the coding efficiency is improved without signaling any information. Since the weight and the offset are obtained in the encoding prediction step and the decoding step, encoder and decoder complexity are increased. This paper proposes two methods for low complexity LIC. The first method is a method of applying illumination compensation with offset only in bi-directional prediction, and the second is a method of applying LIC after weighted average step of reference block obtained by bidirectional prediction. To evaluate the performance of the proposed method, BD-rate is compared with BMS-2.0.1 using B, C, and D classes of MPEG standard experimental image under RA (Random Access) condition. Experimental results show that the proposed method reduces the average of 0.29%, 0.23%, 0.04% for Y, U, and V in terms of BD-rate performance compared to BMS-2.0.1 and encoding/decoding time is almost same. Although the BD-rate was lost, the calculation complexity of the LIC was greatly reduced as the multiplication operation was removed and the addition operation was halved in the LIC parameter derivation process.

• Journal of Communications and Networks
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• v.18 no.2
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• pp.210-217
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• 2016

In this paper, we propose a low complexity multiple-input multiple-output (MIMO) detection algorithm with adaptive interference mitigation in downlink multiuser MIMO (DL MU-MIMO) systems with quantization error of the channel state information (CSI) feedback. In DL MU-MIMO systems using the imperfect precoding matrix caused by quantization error of the CSI feedback, the station receives the desired signal as well as the residual interference signal. Therefore, a complexMIMO detection algorithm with interference mitigation is required for mitigating the residual interference. To reduce the computational complexity, we propose a MIMO detection algorithm with adaptive interference mitigation. The proposed algorithm adaptively mitigates the residual interference by using the maximum likelihood detection (MLD) error criterion (MEC). We derive a theoretical MEC by using the MLD error condition and a practical MEC by approximating the theoretical MEC. In conclusion, the proposed algorithm adaptively performs interference mitigation when satisfying the practical MEC. Simulation results show that the proposed algorithm reduces the computational complexity and has the same performance, compared to the generalized sphere decoder, which always performs interference mitigation.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.