• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.607-610
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• 2007

In this paper, proposes the monitoring system it will be able to trace the executed of each threads in OpenMP based a parallel program. The monitoring system of existing in uses each threads label information and the analysis technique which uses the access-history was most. This has the problem which raises the time and space complexity which is caused by with massive information creation. In this paper, only the thread which includes interest information it creates tracking information with the target. And it provides information which is intuitive to the user it provides the visualization system for to a same time. The visualization model is composed the images-information of a base. This does to be it will be able to understandable a program execute situation using an image processing technique. Therefore, this paper provides the parallel program an effective debugging environment.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1225-1233
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• 1998

An important issue for software developers is to determine when to stop testing the software system and release it to users. Generally the release time is specified by the number of detected faults or the testing time needed to meet the reliability requirement. Software reliability directly depends on the number of remaining or corrected faults. All the detected faults are not always corrected under imperfect debugging environment. We therefore need a new approach to software release policy for imperfect debugging. This paper suggests a software release policy, which guarantees that the reliability requirement has been achieved. The suggested policy is then implemented and illustrated for specific SRGMs.

• The KIPS Transactions:PartA
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• v.18A no.5
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• pp.177-180
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• 2011

In this paper, we present a record-replay technique based on interrupt logging and reproduction. Race conditions have been considered as the main source of nondeterminism in conventional record-replay approaches. However, interrupts are another source of nondeterministic computer system behavior, which must be reproduced at accurate time points, let alone the order of interrupt occurrence. We show that an interrupt-based replayer can be efficiently and effectively implemented by using hardware performance counters and debugging functionality. Experiments also show that the runtime overhead of the interrupt-based replayer is sufficiently low.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.203-203
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• 1992

• The Magazine of the IEIE
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• v.9 no.4
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• pp.40-42
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• 1982

• Journal of the military operations research society of Korea
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• v.17 no.2
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• pp.100-112
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• 1991

Software system is a hierarchical structure with collection of program units. Software system can import external packages globally or locally depending on the usage within a system. If the imported package is used globally, the soft-ware system can be influenced globally by any change of package and programmer's debugging time for the program maintenance will be greater. To solve these problems, it is desirable to use the imported package locally right on the usage point within the system. The model presented in this paper analyzed entity usage of package in structure of program, identified the usage level to obtain localization and provided information for restructure of the program to localize package usage. To obtain localization, it identified declared entities inside the imported package and analyzed the specification and body part of program unit to identify entities referenced from the imported package. The proposed model can be used to improve the maintainability of software system and contributed to reduction of programmer's debugging time in program maintenance.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.143-146
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• 2005

The software reliability growth depends on the testing time because the failure rate varies whether it is long or not. On the other hand, it might be difficult to reduce failure rate for most of the cases are not available for debugging during operational phase, hence, there are some literatures to study that the failure rate is uniform throughout the operational time. The failure rate reduces and the reliability grows with time regardless of debugging. As a result, the products reliability varies with the time duration of these products in point of customer view. The reason of this is that it accumulates the products experience, studies the exact operational method, and then finds and takes action against the fault circumstances. I propose the simple model to represent this status in this paper.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1007-1010
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• 2003

This paper presents in-circuit system-on-chip verification and debugging environment. To maximize the emulation speed, the software part is compiled natively for the host computer and the hardware part is mapped into FPGA. The two parts communicate with each other in transaction level. The operation of the hardware part and the software part is recorded independently during the emulation, and after the emulation is over, they are merged in a waveform to give user a unified view that covers both hardware and software.