• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.59-65
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• 2010

This paper proposes an implementation of a hardware module for transmitting MPEG-2 TS data over the internet protocol (IP)-based network. This implementation consists of two modules; one is an encapsulation module which bridges between n TS packets, where $1\;{\leq}\;n\;{\leq}\;7$, and an IP packets, the other is a packet conversion module which extracts an DSM-CC PS packet from consecutive TS packets and then reconstructing an IP packet. So, these IP packets are carried over 150 megabits per second. Although overall work flow of the proposed DeMUX is based on the reference design of ALTERA, the DeMUX is enhanced by modifying it and performs more functions by adding a packet conversion module. The DeMUX is described by Verilog-HDL (hardware description language) and shows the faithful functionality and throughput through the simulation.

• Current Optics and Photonics
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• v.7 no.2
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• pp.166-175
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• 2023

We theoretically analyze and experimentally demonstrate a polarization-diversified four-channel optical demultiplexer (DeMUX) comprising a hybrid mode conversion-type polarization splitter rotator (PSR) and delayed Mach-Zehnder interferometer optical DeMUX for use in coarse wavelength division multiplexing (CWDM)-based optical interconnect applications. The Si wire-based device fabricated by a complementary metal-oxide semiconductor-compatible process exhibited nearly the same filter spectral response irrespective of the input polarization state under the PSR. The device had an extremely low insertion loss of <1.0 dB, polarization-dependent loss of <1.0 dB, and interchannel imbalance of <0.5 dB, suppressing unwanted wavelength and polarization crosstalk from neighboring channels of <-20 dB at each peak transmission channel grid.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.131-135
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• 2003

WDM(Wavelength division multiplexing) light wave communication system requires MUX/DeMUX and optical filter OADM can be used to extract and add the specific wavelength channel from the transmission line. In this paper, we propose the OADM based on MZI and cascade FBG. It is able to minimize system and reduce sidelobe. So, we have considered MZI structure and 3dB coupler. Using the coupled mode theory. We also analyze out characteristics of OADM and experiment. From results obtained by experiment and computer. Simulation, the proposed OADM with cascade FBG works well. we hope that the obtained result in this paper con be used as the data to design the OADM with cascade FBG.

• International Journal of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.43-48
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• 2019

We design a reconfigurable optical node for metropolitan WDM networks, and numerically study the capability of the node in the optical signal level. Unlike a long-haul WDM system, major limitations of metropolitan WDM systems are power loss, fiber dispersion and optical signal-to-noise ratio(OSNR) degradation due to EDFAs. Therefore, we include the behaviors of transmitter and receiver, and fiber, EDFAs, and optical filters(MUX/DeMux) in numerical simulations with varying parameters over wide range. From simulation results, we can identify the maximum span numbers for OC-48 and OC-192 to achieve $BER<10^{-12}$ using the node structure at various received powers and residual dispersions.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11a
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• pp.187-190
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• 2003

본 논문에서는 다차원 멀티미디어 데이터의 효율적인 스트리밍과, 다차원 입체 시스템 정보의 효율적인 전송을 위한 (역)다중화기를 제안하였다. 제안한 (역)다중화기는 MPEG-2를 TransMux Layer Tool로 이용하였으며 HPEG-4 시스템을 기반으로 설계되었다 다차원 입체 시스템의 구동을 위한 부가 정보는 본 논문에서 제안한 설러 가지 descriptor를 통해, 다차원 멀티미디어 데이터인 다시점 비디오, 스테레오 오디오, 합성 영상과 함께 수신부로 전송된다. 제안한 (역)다중화기는 다차원 입체 시스템에 매우 적합하며, 다른 시스템과의 호환성도 매우 우수하다.

• Journal of Information Display
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• v.11 no.2
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• pp.76-83
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• 2010

This paper presents the multi-user autostereoscopic 3D display system constructed and operated by the authors using the time-multiplexing approach. This prototype has three main advantages over the previous versions developed by the authors: its hardware was simplified as only one optical array is used to create viewing regions in space, a lenticular multiplexing screen is not necessary as images can be produced sequentially on a fast 120Hz LCD with full resolution, and the holographic projector was replaced with a high-frame-rate digital micromirror device (DMD) projector. The whole system in this prototype consists of four major parts: a 120Hz high-frame-rate DMD projector, a 49-element optical array, a 120Hz screen assembly, and a multi-user head tracker. The display images for the left/right eyes are produced alternatively on a 120Hz direct-view LCD and are synchronized with the output of the projector, which acts as a backlight of the LCD. The novel steering optics controlled by the multiuser head tracker system directs the projector output to regions referred to as exit pupils, which are located in the viewers’eyes. The display can be developed in the "hang-on-the-wall"form.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.