• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.401-406
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• 2005

The GFSK Transceiver of 400MHz ISM band for data communication is designed and fabricated. To reduce the occupied bandwidth of transmitted signal, the GFSK modulation is selected. The measured results of fabricated transceiver show the data rate of 2400bps at 8.5kHz bandwidth, frequency deviation of less than $\pm$3kHz, sensitivity of -111dBm, SNR of 21.58dB. The fabricated transceiver is satisfied with the regulation of radio wave and has the good performance. This transceiver is well suited for data communication of 400MHz ISM band.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.3
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• pp.388-396
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• 2010

Generally, flight information is transmitted by voice signal over legacy UHF radio in ground to air communication system. In this paper, we have implemented the transceiver of TDL(tactical data link) which transmits tactical information, such as flight information, using digital signal. For transmitting digital information over radio path, we have designed data modem that is processing CPFSK modulation, and TDMA(Time Division Multiple Access) network for Synchronization among multi user(platform). By simulating aeronautical propagation modeling with the environment of Korea terrain, it is predicted the maximum performance of communication range of the transceiver. As result of the transceiver's aviational boarding test, it is proved that the transceiver of TDL over legacy UHF radio transmits and receives the tactical information in TDMA network within communication range of 160km.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.198-206
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• 2006

The GFSK Transceiver of 400 MHz ISM band for data communication is designed and fabricated. To reduce the occupied bandwidth of transmitted signal, the GFSK modulation is selected. The measured results of fabricated transceiver show the data rate of 2,400 bps at 8.5 kHz bandwidth, frequency deviation of less than ${\pm}3\;kHz$, sensitivity of -107 dBm at SINAD of 20 dB, BER of less than $1.8{\times}10^{-3}$ at -110 dBm input power. The fabricated transceiver is satisfied with the regulation of radio wave and has the good performance.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.29-34
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• 2009

In this paper, we design RF transceiver architecture and building blocks for impulse radio UWB system. Impulse radio UWB signal occupies the wide frequency band which is very low transmission power. So, it can minimize the interference effect with the other system. Using UWB technology, we obtain position awareness service. Therefore, we describe the RF transceiver architecture of direct conversion receiver and define the requirement of RF transceiver. Moreover, we implement a prototype RF transceiver based on the presented standard and verify a function and performance through the wireless data communication and ranging test.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.7
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• pp.2435-2453
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• 2015

Independent component analysis (ICA) is a signal processing technique used for un-mixing of the mixed recorded signals. In wireless communication, ICA is mainly used in multiple input multiple output (MIMO) systems. Most of the existing work regarding the ICA applications in MIMO systems assumed static or quasi static wireless channels. Performance of the ICA algorithms degrades in case of time varying wireless channels and is further degraded if the data block lengths are reduced to get the quasi stationarity. In this paper, we propose an ICA based MIMO transceiver that performs well in time varying wireless channels, even for smaller data blocks. Simulation is performed over quadrature amplitude modulated (QAM) signals. Results show that the proposed transceiver system outperforms the existing MIMO system utilizing the FastICA and the OBAICA algorithms in both the transceiver systems for time varying wireless channels. Performance improvement is observed for different data blocks lengths and signal to noise ratios (SNRs).

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.